DS31407

4

Output Clock Features



Four output clock signals in two groups



separate CMOS/TTL output (≤ 125MHz)





Each output can be any frequency from < 1Hz to max frequency stated above



Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, microprocessor clock

frequencies, and much more



Internal clock muxing allows each output group to slave to its associated DFS block, an APLL output, or

any input clock (after being divided and scaled)



Outputs sourced directly from the APLL have less than 1ps RMS output jitter



Outputs sourced directly from DFS blocks have approximately 40ps RMS output jitter



Optional 32-bit frequency divider per output



8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can

be disciplined by a 2kHz or 8kHz frame sync input



Per-output delay adjustment



Per-output enable/disable



All outputs disabled during reset

General Features



SPI serial microprocessor interface



Four general-purpose I/O pins



Register set can be write protected



Operates from a 12.8MHz, 25.6MHz, 10.24MHz, 20.48MHz, 10MHz, 20MHz, 19.44MHz, or 38.88MHz

local oscillator



On-chip watchdog circuit for the local oscillator



Internal compensation for local oscillator frequency error

Note to readers:

This document is an abridged version of the full data sheet. To request the full data sheet, go to

www.maxim-ic.com/DS31407

and click on Request Full Data Sheet.

ABRIDGED DATA SHEET