Thermal Design

Since the VPS10 includes three channels as shown in the internal equivalent circuit diagram, we first consider a single

channel. The chip temperature of each transistor under actual operating conditions is determined using the following

formula.

Tj (TRi) =

θj-c (TRi) × P

θj-c (Tri): Thermal resistance of an individual transistor

Collector loss for an individual transistor

∆Tc:

Case temperature rise

Ta:

Ambient temperature

The

θj-c (Tri) for each chip is:

θj-c (TR1) to (TR4) = 30°C/W.......................................................... (2)

Although the loss for each transistor in a video pack varies with frequency and is not uniform, if we assume operation at

the maximum operating frequency, f = 100 MHz (clock), then the chips with the largest loss will be the emitter-follower

stage transistors (TR3 and TR4) and that loss will be about 20% of the total loss. Thus from the Pd (shown in the figure)

for a single channel we have:

Here, we must select a heat sink with a capacity

θh such that the Tj of these transistors does not exceed 150°C. Equation

(4) below gives the relationship between

θh and ∆Tc.

∆Tc = Pd (TOTAL) × θh................................................................... (4)

The required

θh is calculated using this equation and equation (1).

No. 5209-3/4

VPS10