IMX53CEC datasheet(3/204 Pages) FREESCALE

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Introduction

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

1.1

Ordering Information

Table 1 provides ordering information.

1.2

Features

The i.MX53xD multimedia applications processor (AP) is based on the ARM Platform, which has the

following features:

•

MMU, L1 instruction and L1 data cache

•

Unified L2 cache

•

Target frequency of the core (including Neon, VFPv3 and L1 cache): 1 GHz

•

Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)

coprocessor supporting VFPv3

•

TrustZone

The memory system consists of the following components:

•

Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

•

Level 2 cache:

— Unified instruction and data (256 Kbyte)

•

Level 2 (internal) memory:

— Boot ROM, including HAB (64 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

— Secure/non-secure RAM (16 Kbyte)

Table 1. Ordering Information

Part Number1

1 Part numbers with a PC prefix indicate non production engineering parts.

Mask Set

Features

Case

Tempera

ture

Range

(

°C)

Package2

2 Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.

PCIMX535DVV1C

N78C

1 GHz, full feature set

-20 to

+85

19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

MCIMX535DVV1C

N78C

1 GHz, full feature set

-20 to

+85

19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

PCIMX538DZK1C

N78C

1 GHz, full feature set

-20 to

+85

12 x 12 mm PoP

MCIMX538DZK1C

N78C

1 GHz, full feature set

-20 to

+85

12 x 12 mm PoP

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