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IMX53CEC Datasheet(PDF) 120 Page - Freescale Semiconductor, Inc |
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IMX53CEC Datasheet(HTML) 120 Page - Freescale Semiconductor, Inc |
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120 / 204 page ![]() i.MX53xD Applications Processors for Consumer Products, Rev. 2 120 Freescale Semiconductor Electrical Characteristics 4.7.13.1.1 Reference Clock Jitter Measurement The total phase jitter on the reference clock is specified at 3 ps RMS. There are numerous ways to measure the reference clock jitter, one of which is as follows. Using a high-speed sampling scope (20 GSamples/s), 1 million samples of the differential reference clock are taken, and the zero-crossing times of each rising edge are calculated. From the zero-crossing data, an average reference clock period is calculated. This average reference clock period is subtracted from each sequential, instantaneous period to find the difference between each reference clock rising edge and the ideal placement to produce the phase jitter sequence. The power spectral density (PSD) of the phase jitter is calculated and integrated after being weighted with the transfer function shown in Figure 74. The square root of the resultant integral is the RMS total phase jitter. Figure 74. Weighting Function for RMS Phase Jitter Calculation 4.7.13.2 Transmitter and Receiver Characteristics The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA specification. The following subsections provide values obtained from a combination of simulations and silicon characterization. NOTE The tables in the following sections indicate any exceptions to the SATA specification or aspects of the SATA PHY that exceed the standard, as well as provide information about parameters not defined in the standard. 4.7.13.2.1 SATA PHY Transmitter Characteristics Table 78 provides specifications for SATA PHY transmitter characteristics. Table 78. SATA2 PHY Transmitter Characteristics Parameters Symbol Min Typ Max Unit Transmit common mode voltage VCTM 0.4 — 0.6 V Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) —–0.5 — 0.5 dB |
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