IMX53CEC datasheet(127/204 Pages) FREESCALE

127 / 204 page

Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

127

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

•

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

•

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

SS17

(Tx) CK high to STXD high/low

—

15.0

SS18

(Tx) CK high to STXD high impedance

—

15.0

SS19

STXD rise/fall time

—

6.0

Synchronous Internal Clock Operation

SS42

SRXD setup before (Tx) CK falling

10.0

—

SS43

SRXD hold after (Tx) CK falling

0.0

—

SS52

—

25.0

Table 83. SSI Transmitter Timing with Internal Clock (continued)

Parameter

Min

Max

Unit

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