MPC8548E datasheet(69/143 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

PCI Express

16.3

SerDes Transmitter and Receiver Reference Circuits

Figure 47 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 47. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express, Serial Rapid IO, or SGMII) in this document based on the application usage:

•

Section 17, “PCI Express”

•

Section 18, “Serial RapidIO”

Note that external an AC coupling capacitor is required for the above three serial transmission protocols

with the capacitor value defined in the specification of each protocol section.

17 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8548E.

17.1

DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 16.2, “SerDes Reference Clocks.”

17.2

AC Requirements for PCI Express SerDes Clocks

Table 55 lists the AC requirements for the PCI Express SerDes clocks.

Table 55. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typ

Max

Unit

Notes

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles.

—

100

—

tREFPJ

Phase jitter. Deviation in edge location with respect to mean edge

location.

–50

—

Note:

1. Typical based on

PCI Express Specification 2.0.

SD_TX

SD_RX

Receiver

Transmitter

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