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LPC2212 Datasheet(PDF) 39 Page - NXP Semiconductors

Part # LPC2212
Description  Single-chip 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC
PDF  47 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2212 Datasheet(HTML) 39 Page - NXP Semiconductors

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LPC2212_2214
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
39 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
[1]
Except on initial access, in which case the address is set up Tcy(CCLK) earlier.
[2]
Tcy(CCLK) = 1⁄CCLK.
[3]
Latest of address valid, CS LOW, OE LOW to data valid.
[4]
Address valid to data valid.
[5]
Earliest of CS HIGH, OE HIGH, address change to data invalid.
[1]
See the LPC2114/2124/2212/2214 User Manual for a description of the WSTn bits.
tBLSHDNV
BLS HIGH to data invalid
time
[2] (2
 T
cy(CCLK))  5-
(2
 T
cy(CCLK))+5
ns
tCHDV
XCLK HIGH to data valid
time
--
10
ns
tCHWEL
XCLK HIGH to WE LOW
time
--
10
ns
tCHBLSL
XCLK HIGH to BLS LOW
time
--
10
ns
tCHWEH
XCLK HIGH to WE HIGH
time
--
10
ns
tCHBLSH
XCLK HIGH to BLS HIGH
time
--
10
ns
tCHDNV
XCLK HIGH to data invalid
time
--
10
ns
Table 10.
External memory interface dynamic characteristics …continued
CL =25 pF; Tamb =40 C.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Table 11.
Standard read access specifications
Access cycle
Max frequency
WST[1] setting
WST
 0; round up to
integer
Memory access time requirement
standard read
standard write
burst read - initial
burst read - subsequent 3
N/A
f
MAX
2WST1
+
t
RAM
20 ns
+
--------------------------------
WST1
t
RAM
20 ns
+
t
cy CCLK

--------------------------------
2
–
t
RAM
t
cy CCLK

2WST1
+

20 ns
–
f
MAX
1WST2
+
t
WRITE
5 ns
+
----------------------------------
WST2
t
WRITE
t
CYC
5
+
–
t
cy CCLK

-------------------------------------------
t
WRITE
t
cy CCLK

1WST2
+

5 ns
–
f
MAX
2WST1
+
t
INIT
20 ns
+
--------------------------------
WST1
t
INIT
20 ns
+
t
cy CCLK

--------------------------------
2
–
t
INIT
t
cy CCLK

2WST1
+

20 ns
–
f
MAX
1
t
ROM
20 ns
+
---------------------------------
t
ROM
t
cy CCLK

20 ns
–



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