AD9434 datasheet(25/28 Pages) AD

25 / 28 page

AD9434

Rev. A | Page 25 of 28

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table (see Table 13) has eight

address locations. The memory map is roughly divided into

three sections: chip configuration register map (Address 0x00 to

Address 0x02), transfer register map (Address 0xFF), and ADC

functions register map (Address 0x08 to Address 0x2A).

The Addr. (Hex) column of the memory map indicates the

column shows the default hexadecimal value that is already

written into the register. The Bit 7 (MSB) column is the start of

the default hexadecimal value given. For example, Hexadecimal

Address 0x2A, OVR_CONFIG, has a hexadecimal default value

of 0x01. This means that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0,

Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in

binary. The default value enables the OR± output. Overwriting

this default so that Bit 0 = 0 disables the OR± output. For more

information on this and other functions, consult the AN-877

Application Note, Interfacing to High-Speed ADCs via SPI® at

www.analog.com.

RESERVED LOCATIONS

Undefined memory locations should not be written to other

than with the default values suggested in this data sheet. Addresses

that have values marked as 0 should be considered reserved and

have a 0 written into their registers during power-up.

DEFAULT VALUES

Exiting out of reset, critical registers are preloaded with default

values. These values are indicated in Table 13. Other registers

do not have default values and retain the previous value when

exiting reset.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Table 13. Memory Map Register

Addr.

(Hex)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default Notes/

Comments

Chip Configuration Registers

CHIP_PORT_CONFIG

LSB

first

Soft

reset

Soft

reset

LSB

first

0x18

The nibbles

should be

mirrored by the

user so that LSB

or MSB first

mode registers

correctly,

regardless of

shift mode.

CHIP_ID

8-bit chip ID, Bits[7:0] = 0x6A

Read

only

Default is a

unique chip ID,

different for

each device.

This is a read-

only register.

CHIP_GRADE

Speed grade:

00 = 500 MSPS

01 = 370 MSPS

Read

only

Child ID used to

differentiate

graded devices.

Transfer Register

DEVICE_UPDATE

transfer

0x00

Synchronously

transfers data

from the master

shift register to

the slave.

ADC Functions Registers

Modes

PDWN:

0 = full

(default)

1 =

standby

Internal power-down mode:

000 = normal (power-up,

default)

001 = full power-down

010 = standby

011 = normal (power-up)

Note that external PDWN pin

overrides this setting

0x00

Determines

various generic

modes of chip

operation.

AD9434 Datasheet(PDF) 25 Page - Analog Devices

AD9434 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL