AD9434 datasheet(26/28 Pages) AD

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AD9434

Rev. A | Page 26 of 28

Addr.

(Hex)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default Notes/

Comments

Offset

8-bit device offset adjustment [7:0]

0111 1111 = +127 codes

0000 0000 = 0 codes

1000 0000 = −128 codes

0x00

Device offset

trim: codes are

relative to the

output

resolution.

TEST_IO

(For user-defined

mode only, set

Bits[3:0] = 1000)

00 = Pattern 1 only

01 = toggle P1/P2

10 = toggle

P1/0000

11 = toggle P1/P2/

0000

Reset

PN23

gen:

1 = on

0 = off

(default)

Reset

PN9

gen:

1 = on

0 = off

(default)

Output test mode:

0000 = off (default)

0001 = midscale short

0010 = +FS short

0011 = −FS short

0100 = checkerboard output

0101 = PN23 sequence

0110 = PN9

0111 = one/zero word toggle

1000 = user defined

1001 = unused

1010 = unused

1011 = unused

1100 = unused

(Format determined by OUTPUT_MODE)

0x00

When set, the

test data is

placed on the

output pins in

place of normal

data.

Set pattern

values:

P1 = Reg 0x19,

Reg 0x1A

P2 = Reg 0x1B,

Reg 0x1C.

AIN_CONFIG

Analog

input

disable:

1 = on

0 = off

(default)

0x00

OUTPUT_MODE

Output

enable:

0 =

enable

(default)

1 =

disable

DDR:

1 =

enabled

0 =

disabled

(default)

Output

invert:

1 = on

0 = off

(default)

Data format select:

00 = offset binary

(default)

01 = twos

complement

10 = Gray code

0x00

OUTPUT_ADJUST

LVDS

course

adjust:

0 =

3.5 mA

(default)

1 =

2.0 mA

LVDS fine adjust:

001 = 3.50 mA

010 = 3.25 mA

011 = 3.00 mA

100 = 2.75 mA

101 = 2.50 mA

110 = 2.25 mA

111 = 2.00 mA

0x00

OUTPUT_PHASE

Output

clock

polarity

1 =

inverted

0 =

normal

(default)

0x00

FLEX_OUTPUT_DELAY

Output clock delay:

0000 = 0

0001 = −1/10

0010 = −2/10

0011 = −3/10

0100 = reserved

0101 = +5/10

0110 = +4/10

0111 = +3/10

1000 = +2/10

1001 = +1/10

0x00

Shown as

fractional value

of sampling

clock period

that is

subtracted or

added to initial

tSKEW, see

Figure 2

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