CY22150

Document #: 38-07104 Rev. *K

Page 13 of 18

AC Electrical Characteristics

Parameter[7]

Name

Description

Min

Typ.

Max

Unit

t1

Output Frequency,

Commercial Temp

Clock output limit, 3.3 V

0.08 (80 kHz)

–

200

MHz

Clock output limit, 2.5 V

0.08 (80 kHz)

–

166.6

MHz

Output Frequency,

Industrial Temp

Clock output limit, 3.3 V

0.08 (80 kHz)

–

166.6

MHz

Clock output limit, 2.5 V

0.08 (80 kHz)

–

150

MHz

Output Duty Cycle

Duty cycle is defined in Figure 8 on page 11;

t1/t2

45

50

55

%

Output Duty Cycle

Duty cycle is defined in Figure 8; t1/t2

40

50

60

%

Rising Edge Slew

Defined in Figure 9

0.6

1.2

–

V/ns

Falling Edge Slew

Defined in Figure 9

0.6

1.2

–

V/ns

Rising Edge Slew

Output dlock rise time, 20% to 80% of

0.8

1.4

–

V/ns

Falling Edge Slew

Defined in Figure 9

0.8

1.4

–

V/ns

t5[8]

Skew

Output-output skew between related outputs

–

–

250

ps

t6[9]

Clock Jitter

Peak-to-peak period jitter

–

250

–

ps

t10

PLL Lock Time

–

0.30

3

ms

7. Not 100% tested, guaranteed by design.

8. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram on page 1 for more information.

Device Characteristics

Parameter

Name

Value

Unit

θ

JA

Theta JA

115

°C/W

Complexity

Transistor Count

74,600

Transistors

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