CY29972

Document #: 38-07290 Rev. *D

Page 8 of 13

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Input Low voltage

–0.8

V

Input High voltage

2.0

–

V

Input Low current[6]

–

–

–120

µA

Input High current

–

–

10

µA

Output Low voltage[7]

IOL = 20 mA

–

–

0.5

V

Output High voltage[7]

IOH = –20 mA

2.4

–

–

V

Quiescent supply current

–

10

15

mA

PLL supply current

–

15

20

mA

Dynamic supply current

QA and QB at 60 MHz, QC at 120 MHz, CL = 30 pF

–

225

–

mA

QA and QB at 25 MHz, QC at 50 MHz, CL = 30 pF

–

125

–

Input pin capacitance

–

4

–

pF

Parameter

Description

Conditions

Min

Typ

Max

Unit

Tr / Tf

TCLK input rise/fall

–

–

3.0

ns

Fref

Reference input frequency

Note 9

–

Note 9

MHz

Fxtal

Crystal Oscillator Frequency

see Table 2

10–25

MHz

FrefDC

Reference input duty cycle

25

–

75

%

Fvco

PLL VCO lock range

200

–

480

MHz

Tlock

Maximum PLL lock time

–

–

10

ms

Tr / Tf

Output clocks rise / fall time[10]

0.8 V to 2.0 V

0.15

–

1.2

ns

Fout

Maximum Output Frequency

Q (³2)

–

–

125

MHz

Q (³4)

–

–

120

Q (³6)

–

–

80

Q (³8)

–

–

60

FoutDC

Output duty cycle[10]

TCYCLE/2 – 750

–

TCYCLE/2 + 750

ps

tpZL, tpZH

Output enable time[10](all outputs)

2

–

10

ns

tpLZ, tpHZ

Output disable time[10](all outputs)

2

–

8

ns

TCCJ

Cycle to cycle jitter[10](peak to peak)

–

± 100

–

ps

TSKEW

Any output to any output skew[10,11]

–

250

350

ps

Tpd

Propagation delay[11,12]

QFB = (³8)

–270

130

530

ps

–330

70

470

Notes

6. Inputs have pull-up/pull-down resistors that effect input current.

7. Driving series or parallel terminated 50

8. Parameters are guaranteed by design and characterization. Not 100% tested in production.

9. Maximum and minimum input reference is limited by VC0 lock range.

10. Outputs loaded with 30 pF each.

11. 50

12. Tpd is specified for a 50-MHz input reference. Tpd does not include jitter.

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