AD7291

Rev. 0 | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

14

13

12

1

3

4

SDA

15

SCL

AS1

ALERT

11

AS0

2

5

AD7291

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED METAL PADDLE ON THE BOTTOM

OF THE LFCSP PACKAGE SHOULD BE SOLDERED

TO PCB GROUND FOR PROPER HEAT DISSIPATION

AND PERFORMANCE.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1 to 5,

18 to 20

Analog Inputs. The AD7291 has eight single-ended analog inputs that are multiplexed into the on-chip track-and-

hold amplifier. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should

be connected to GND1 to avoid noise pickup.

6

GND1

Ground. Ground reference point for the internal reference circuitry on the AD7291. All analog input signals and

the external reference signals should be referred to this GND1 voltage. The GND1 pin should be connected to the

ground plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V

capacitor.

7

Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin.

Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest

of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For best

performance, it is recommended to use a 10 μF decoupling capacitor on this pin to GND1. The internal reference

can be disabled and an external reference supplied to this pin if required. The input voltage range for the external

reference is 2.0 V to 2.5 V.

8

Decoupling Capacitor Pin. Decoupling capacitors (1 μF recommended) are connected to this pin to decouple the

internal LDO.

9

GND

Ground. Ground reference point for all analog and digital circuitry on the AD7291. The GND pin should be con-

nected to the ground plane of the system. All ground pins should ideally be at the same potential and must not be

10

Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 μF and 100 nF decoupling capacitors.

11, 13

AS0, AS1

for details. The device address depends on the voltage applied to these pins.

12

ALERT

Digital Output. This pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion

14

SDA

Digital Input/Output. Serial bus bidirectional data. This open-drain output requires a pull-up resistor. The output coding

is straight binary for the voltage channels and twos complement for the temperature sensor result.

15

SCL

compatible with both 100 kHz and 400 kHz operating modes.

16

Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface operates.

This pin should be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and may be less than the

17

PD/RST

Power-Down Pin. This pin places the part into a full power-down mode and enables power conservation when

operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a

maximum of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the device in

full power-down mode, the analog inputs must be returned to 0 V.

EPAD

EPAD

Exposed Paddle. The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB

ground for proper functionality and heat dissipation.