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AD7291 Datasheet(PDF) 19 Page - Analog Devices |
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AD7291 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 28 page ![]() AD7291 Rev. 0 | Page 19 of 28 Table 17. TSENSE Conversion Result Register (First Read) MSB D15 D14 D13 D12 D11 D10 D9 D8 ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8 Table 18. TSENSE Result Register (Second Read) LSB D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0 TSENSE AVERAGE RESULT REGISTER (0x03) The TSENSE average result register is a 16-bit read-only register used to store the average result from the internal temperature sensor. This register stores the average temperature readings from the ADC in an 11-bit twos complement format, D11 to D0, and uses Bit D15 to Bit D12 to store the channel address bits. The TSENSE average result register is updated after every TSENSE conversion is completed. The first TSENSE average conversion result given by the AD7291 after averaging is enabled is the actual first TSENSE conversion result. Table 13 details the temperature data format, which applies to the internal temperature sensor. See the Temperature Sensor Averaging section for more details. Table 19. TSENSE Average Result Register (First Read) MSB D15 D14 D13 D12 D11 D10 D9 D8 ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8 Table 20. TSENSE Average Result Register (Second Read) LSB D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0 LIMIT REGISTERS (0x04 TO 0x1E) The AD7291 has nine pairs of limit registers. Each pair stores high and low conversion limits for each analog input channel and the internal temperature sensor. Each pair of limit registers has one associated hysteresis register. All 27 registers are 16 bits wide; only the 12 LSBs of the registers are used for the AD7291. The four MSBs, D15 and D12, in these registers should contain 0s. During power-up, the contents of the DATAHIGH register for each analog voltage channel is full scale (0x0FFF), while the default contents of the DATALOW voltage channels registers is zero scale (0x0000). The output coding of the AD7291 is twos complement for the temperature conversion result. The default content for the TSENSE DATAHIGH register is 0x07FF, while the default content of the TSENSE DATALOW register is 0x0800. The AD7291 signals an alert in hardware if the conversion result moves outside the upper or lower limit set by the limit registers. DATAHIGH Register The DATAHIGH registers for CH0 to CH7 and the internal temperature sensor are 16-bit read/write registers; only the 12 LSBs of each register are used. Bit D15 to Bit D12 are not used in the register and are set to 0s. This register stores the upper limit that activates the ALERT output. If the value in the conversion result register is greater than the value in the DATAHIGH register, an ALERT occurs for that channel. When the conversion result returns to a value at least N LSBs below the DATAHIGH register value, the ALERT output pin is reset. The value of N is taken from the hysteresis register associated with that channel. The ALERT pin can also be reset by writing to Bit D2 in the command register. Table 21. DATAHIGH Register (First Read/Write) MSB D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 B11 B10 B9 B8 Table 22. DATAHIGH Register (Second Read/Write) LSB D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0 DATALOW Register The DATALOW register for each channel is a 16-bit read/write register; only the 12 LSBs of each register are used. Bit D15 to Bit D12 are not used in the register and are set to 0s. The register stores the lower limit that activates the ALERT output. If the value in the TSENSE conversion result register is less than the value in the DATALOW register, an ALERT occurs for that channel. When the conversion result returns to a value at least N LSBs above the DATALOW register value, the ALERT output pin is reset. The value of N is taken from the hysteresis register associated with that channel. The ALERT output pin can also be reset by writing to Bit D2 in the command register. Table 23. DATALOW Register (First Read/Write) MSB D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 B11 B10 B9 B8 Table 24. DATALOW Register (Second Read/Write) LSB D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0 |
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