PCA9601DP datasheet(4/32 Pages) NXP

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PCA9601

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Product data sheet

Rev. 2 — 6 May 2011

4 of 32

NXP Semiconductors

PCA9601

Dual bidirectional bus buffer

Functional description

Refer to Figure 1 “Block diagram of PCA9601”.

The PCA9601 has two identical buffers allowing buffering of SDA and SCL I2C-bus

signals. Each buffer is made up of two logic signal paths, a forward path from the I2C-bus

interface, pins SX and SY which drive the buffered bus, and a reverse signal path from the

buffered bus input, pins RX and RY to drive the I2C-bus interface. These paths:

• sense the voltage state of I2C-bus pins SX (and SY) and transmit this state to pin TX

(and TY respectively), and

• sense the state of pins RX and RY and pull the I2C-bus pin LOW whenever pin RX or

pin RY is LOW.

The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is

identical.

7.1 Static level offset card side

The I2C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based

systems.

The logic threshold voltage levels at SX on this I2C-bus are independent of the IC supply

voltage VCC. The maximum I2C-bus supply voltage is 15 V.

7.1.1 Fast-mode operation

When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal

3 mA with a VOL of 0.74 V maximum. That guarantees compliance with the Fast-mode

I2C-bus specification for all I2C-bus voltages greater than 3 V, as well as compliance with

SMBus or other systems that use TTL switching levels.

SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of

typically 300

μA (maximum 1 mA at −40 °C). When selecting the pull-up for the bus at SX,

the sink capability of other connected drivers should be taken into account. Most TTL

devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the

requirement to ensure the 0.8 V TTL LOW.

For Fast-mode I2C-bus operation, the other connected I2C-bus parts may have the

minimum sink capability of 3 mA. SX sources typically 300

μA (maximum 1 mA at −40 °C),

which forms part of the external driver loading. When selecting the pull-up it is necessary

to subtract the SX pin pull-up current, so, worst-case at

−40 °C, the allowed pull-up can be

limited (by external drivers) to 2 mA.

7.1.2 Fast-mode Plus operation

When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher

specified sink capability may be used. PCA9601 has a guaranteed sink capability of

15 mA at VOL = 1 V maximum over 0 °C to 85 °C. That 1 V complies with the bus LOW

requirement (0.25Vbus) of any Fm+ bus operating at 4 V or greater. Since the other

connected Fm+ devices have a drive capability greater than 20 mA, the pull-up may be

selected for 15 mA sink current at VOL = 1 V. For a nominal 5 V bus (5.5 V maximum) the

allowed pull-up is (5.5 V

− 1 V) / 15 mA = 300 Ω. With 300 Ω pull-up, the Fm+ rise time of

120 ns maximum can be met with total bus loading up to 470 pF.

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