PCA9564_06 datasheet(5/32 Pages) PHILIPS

5 / 32 page

Philips Semiconductors

Product data sheet

PCA9564

Parallel bus to I2C-bus controller

2006 Sep 01

FUNCTIONAL DESCRIPTION

General

The PCA9564 acts as an interface device between standard

high-speed parallel buses and the serial I2C-bus. On the I2C-bus, it

can act either as master or slave. Bidirectional data transfer between

the I2C-bus and the parallel-bus microcontroller is carried out on a

byte-wise basis, using either an interrupt or polled handshake.

Internal Oscillator

The PCA9564 contains an internal 9 MHz oscillator which is used

for all I2C timing. The oscillator requires up to 500

µs to start-up

after ENSIO bit is set to “1”.

Registers

The PCA9564 contains four registers which are used to configure

the operation of the device as well as to send and receive serial data.

The registers are selected by setting pins A0 and A1 to the

appropriate logic levels before a read or write operation is executed.

CAUTION:

Do not write to I2C registers while the I2C-bus is busy

and the SIO is in master or addressed slave mode.

NAME

FUNCTION

READ/

WRITE

DEFAULT

I2CSTA

Status

F8h

I2CTO

Time-out

FFh

I2CDAT

Data

R/W

00h

I2CADR

Own address

R/W

00h

I2CCON

Control

R/W

00h

The Time-out Register, I2CTO: The time-out register is used to

determine the maximum time that SCL is allowed to be LOW before

the I2C state machine is reset.

When the I2C interface is operating, I2CTO is loaded in the time-out

counter at every SCL transition.

I2CTO

Time-out value

TO6

TO5

TO4

TO3

TO2

TO1

TO0

The most significant bit of I2CTO (TE) is used as a time-out

enable/disable. A “1” will enable the time-out function. The time-out

period = (I2CTO[6:0] + 1)

× 113.7 µs. The time-out value may vary

some and is an approximate value.

The time-out register can be used in the following cases:

1. When the SIO, in the master mode, wants to send a START

condition and the SCL line is held LOW by some other device.

The SIO waits a time period equivalent to the time-out value for

the SCL to be released. In case it is not released, the SIO

concludes that there is a bus error, loads 90H in the I2CSTA

SDA lines. After the microcontroller reads the status register, it

needs to send an external reset in order to reset the SIO.

2. In the master mode, the time-out feature starts every time the SCL

goes LOW. If SCL stays LOW for a time period equal to or greater

than the time-out value, the SIO concludes there is a bus error

and behaves in the manner described above.

3. In case of a forced access to the I2C-bus. (See more details on

page 15.)

The Address Register, I2CADR: I2CADR is not affected by the

SIO hardware. The contents of this register are irrelevant when SIO

is in a master mode. In the slave modes, the seven most significant

bits must be loaded with the microcontroller’s own slave address.

I2CADR

own slave address

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

The most significant bit corresponds to the first bit received from the

I2C-bus after a start condition. A logic 1 in I2CADR corresponds to a

HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW

level on the bus. The least significant bit is not used but should be

programmed with a ‘0’.

The Data Register, I2CDAT: I2CDAT contains a byte of serial data

to be transmitted or a byte which has just been received. In master

mode, this includes the slave address that the master wants to send

out on the I2C-bus, with the most significant bit of the slave address

in the SD7 bit position and the Read/Write bit in the SD0 bit position.

The CPU can read from and write to this 8-bit register while it is not

in the process of shifting a byte. This occurs when SIO is in a

defined state and the serial interrupt flag is set. Data in I2CDAT

remains stable as long as SI is set. Whenever the SIO generates an

interrupt, the I2CDAT registers contain the data byte that was just

transferred on the I2C-bus.

NOTE: The I2CDAT register will capture the serial address as data

when addressed via the serial bus. Also, the data register will

continue to capture data from the serial bus during 38H so the

I2CDAT register will need to be reloaded when the bus becomes

free.

I2CDAT

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

• SD7 - SD0:

Eight bits to be transmitted or just received. A logic 1 in I2CDAT

corresponds to a HIGH level on the I2C-bus, and a logic 0

corresponds to a LOW level on the bus.

The Control Register, I2CCON: The microcontroller can read from

and write to this 8-bit register. Two bits are affected by the SIO

hardware: the SI bit is set when a serial interrupt is requested, and

the STO bit is cleared when a STOP condition is present on the

I2C-bus. A write to the I2CCON register clears the SI bit and causes

the Serial Interrupt line to be de–asserted and the next clock pulse

on the SCL line to be generated. Since none of the registers should

be written to via the parallel interface once the Serial Interrupt line

has been de-asserted, all the other registers that need to be

modified should be written to before the content of the I2CCON

I2CCON

ENSIO

STA

STO

CR1

CR0

CR2

• ENSIO, THE SIO ENABLE BIT

ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in a

high impedance state. SDA and SCL input signals are ignored, SIO

is in the “not addressed” slave state.

ENSIO = “1”: When ENSIO is “1”, SIO is enabled.

After the ENSIO bit is set, it takes 500

µs for the internal oscillator to

start up, therefore, the PCA9564 will enter either the master or the

slave mode after this time. ENSIO should not be used to temporarily

PCA9564 Datasheet(PDF) 5 Page - NXP Semiconductors

PCA9564 Datasheet(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL