150mA ULTRA LOW DROPOUT,

LOW NOISE REGULATOR

© 2000 SEMTECH CORP.

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC8863

March 1, 2000

8

bility may be improved by increasing C2 to 2.2µF and

reducing R2 to 10k

Ω. See “Component Selection -

General” for input capacitor requirements.

Thermal Considerations

The worst-case power dissipation for this part is given

by:

For all practical purposes, it can be reduced to:

Looking at a typical application:

VIN

VO = 3V - 3.5% worst-case

I

T

Using this figure, we can calculate the maximum ther-

mal impedance allowable to maintain T

With the standard SOT-23-5 Land Pattern shown at

the end of this datasheet, and minimum trace widths,

the thermal impedance junction to ambient for SC8863

is 256°C/W. Thus with no additional heatsinking,

T

The junction temperature can be further reduced by

the use of larger trace widths, and connecting pcb cop-

per area to the GND pin (pin 2), which connectes di-

rectly to the device substrate. Adding approximately

one square inch of pcb copper to pin 2 will reduce

θ

proximately 110°C, for example. Lower junction tem-

peratures improve overall output voltage accuracy. A

sample pcb layout for the Internally Preset Output Volt-

age circuit on page 2 is shown in Figure 2 below.

Layout Considerations

While layout for linear devices is generally not as criti-

cal as for a switching application, careful attention to

detail will ensure reliable operation. See Figure 2 below

for a sample layout.

1) Attaching the part to a larger copper footprint will

enable better heat transfer from the device, especially

on PCBs where there are internal ground and power

planes.

2) Place the input and output capacitors (and the ca-

pacitor from OUT to SET for adjustable applications)

close to the device for optimal transient response and

device behaviour.

3) Connect all ground connections directly to the

ground plane. If there is no ground plane, connect to a

common local ground point before connecting to board

ground.

W

/

C

332

196

.

0

85

150

P

T

T

)

MAX

(

D

)

MAX

(

A

)

MAX

(

J

)

MAX

)(

A

J

(

°

=

−

=

−

=

θ

−

()

(

)

()

)

MAX

(

Q

)

MAX

(

)

MAX

(

O

MIN

MAX

)

MAX

(

D

I

VIN

I

VO

VIN

P

•

+

•

−

=

()

(

)

()

)

MAX

(

O

MIN

MAX

)

MAX

(

D

I

VO

VIN

P

•

−

=

()

mW

196

150

.

0

895

.

2

2

.

4

P

)

MAX

(

D

=

•

−

=

Top Copper

Top Silk Screen

Figure 2: Suggested pcb layout based upon internally preset output voltage application on page 2.

NOTES:

(1) All vias go to the ground plane.

(2) Copper area on pin 2 is recommended, but not required. Connect to the ground plane with a via or vias.