LH543621 datasheet(21/57 Pages) SHARP

21 / 57 page

PORT

COMMAND

BITS

CODE

VALUE

AFTER

RESET

FLAG

AFFECTED,

IF ANY

DESCRIPTION

NOTES

A, B

PFA, PFB

EVEN parity in effect.

A correct 9-bit byte has an even

number of ones.

ODD parity in effect.

A correct 9-bit byte has an odd number

of ones.

L–

Disable Port A parity generation.

No overwriting of parity bits.

Enable Port A parity generation.

Parity bit over eight least-significant bits

of each byte is overwritten into the

most-significant bit of that byte.

PFA

Port A parity-error flag operates

’flowthrough.’

PFA is subject to transient glitches

while data bus is changing.

Port A parity-error flag is latched

by CKA.

PFA is subject to transient glitches

while data bus is changing.

EF2

Set by

↑ CKA, reset by ↑ CKB.

Asynchronous flag clocking.

Set and reset by

↑ CKA.

Synchronous flag clocking.

AE2

Set by

↑ CKA, reset by ↑ CKB.

Asynchronous flag clocking.

Set and reset by

↑ CKB.

Synchronous flag clocking.

05, 06

HF1

Set by

↑ CKA, reset by ↑ CKB.

Asynchronous flag clocking.

Set and reset by

↑ CKB.

Synchronous flag clocking by

Port B clock.

HL, HH

Set and reset by

↑ CKA.

Synchronous flag clocking by

Port A clock.

AF1

Set by

↑ CKA, reset by ↑ CKB.

Asynchronous flag clocking.

Set and reset by

↑ CKA.

Synchronous flag clocking.

FF1

Set by

↑ CKA, reset by ↑ CKB.

Asynchronous flag clocking.

Set and reset by

↑ CKA.

Synchronous flag clocking.

PFB

Parity check computed over all

four bytes of each word.

Full-word parity-error indication

regardless of WS1 – WS0 setting.

Parity check computed over half-

word or single-byte according to

WS1 – WS0 setting.

Full-word, half word, or single-byte

parity-error indication according to

WS1 – WS0 setting.

L–

Disable Port B parity generation.

No overwriting of parity bits.

Enable Port B parity generation.

Parity bit over eight least-significant bits

of each byte is overwritten into the

most-significant bit of that byte.

PFB

Port B parity-error flag operates

’flowthrough’.

PFB is subject to transient glitches

while data bus is changing.

Port B parity-error flag is latched

by CKB.

PFB remains steady until its value

should change.

EF1

Set by

↑ CKB, reset by ↑ CKA.

Asynchronous flag clocking.

Set and reset by

↑ CKB.

Synchronous flag clocking.

AE1

Set by

↑ CKB, reset by ↑ CKA.

Asynchronous flag clocking.

Set and reset by

↑ CKA.

Synchronous flag clocking.

14, 15

HF2

Set and reset by

↑ CKA.

Asynchronous flag clocking.

Set and reset by

↑ CKA.

Synchronous flag clocking by Port A

clock.

HL, HH

Set and reset by

↑ CKA.

Synchronous flag clocking by Port B

clock.

Table 5. Control-Register Format

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

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