LH543621 datasheet(39/57 Pages) SHARP

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543611-48

CKA (CKB)

R/WA (R/WB)

R/WB (R/WA)

ENB (ENA)

tRWS

tES

tEH

tRQS

tRQH

tHF

tRWS

tRWH

tES

tEH

tRQS

tRQH

tHF

tSKEW2 (4)

tRWH

REQB (REQA)

ENA (ENB)

REQA (REQB)

CKB (CKA)

HF2 (HF1)

NOTES:

1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.

A0B is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.

Parameters with parentheses apply to FIFO #1 operation.

3. Both assertion and deassertion of the Half-Full Flags are controlled

entirely by rising clock edges, rather than by falling clock edges.

4. tSKEW2 is the minimum time between a falling CKB (CKA) edge

and a rising CKA (CKB) edge for HF to change predictably during

the current clock cycle. If the time between the falling edge of

CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW2,

then it is not guaranteed that HF will change state until the next

following CKA (CKB) edge.

Figure 27.

Half-Full Flag Timing, When Synchronized

to a Port Clock Doing Reading

TIMING DIAGRAMS (cont’d)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

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