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RFPA0133

DS100803

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Note: The 8dB and 16dB gain steps are approximate for small signal operation. As the device compresses, the values of the

gain steps compress as well. The output power table on page two shows the effect of the gain steps for saturated (0dBm input)

operation.

Pin

Function

Description

1,4,5,

7,8,

11, 15

NC

These pins may be left unconnected or soldered to ground.

2

GND

Ground connection. Keep traces physically short and connect immediately to the ground plane for best perfor-

mance.

3

RF IN

Amplifier RF input. The amplifier does not contain internal DC blocking and, therefore, should be externally DC

blocked before connecting to any device which has DC present or which contains a DC path to ground.

6

VPD

Power down control voltage. When this pin is at 0V, the device will be in power down mode, dissipating minimum

DC power. When this pin is at 3V the device will be in full power mode delivering maximum gain and output

power capability. This pin should not, in any circumstance, be higher than 3.3V. This pin should also have an

9,10

RF

OUT/VCC2

Amplifier RF output. This is an unmatched collector output of the final amplifier transistor. Bias for the final

power amplifier output transistor must also be provided through one of these pins. Pins 9 and 10 should be

used for the RF output with a matching network that presents the optimum load impedance to the PA for maxi-

mum power and efficiency, as well as providing DC blocking at the output.

12

G8

RF output power gain control 8dB bit (see specification table for logic). The control voltage at this pin should

never exceed 3.3V and a logic high should be at least 1.7V. This pin should also have an external UHF bypassing

capacitor. See note.

13

G16

RF output power gain control 16dB bit (see specification table for logic). The control voltage at this pin should

never exceed 3.3V and a logic high should be at least 1.7V. This pin should also have an external UHF bypassing

capacitor. See note.

14

VCC1

Positive supply for the first stage (driver) amplifier. This is an unmatched transistor collector output.

16

VBIAS

Positive supply for the bias circuits. This pin should be bypassed with a single UHF capacitor, placed as close as