LPC11CX2 datasheet(21/62 Pages) NXP

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LPC11CX2_CX4

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Product data sheet

Rev. 3 — 27 June 2011

21 of 62

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.11.2.6

Time-out function

A ‘TXD dominant time-out’ timer is started when the CAN_TXD signal of the C_CAN

controller is set LOW. If the LOW state on the CAN_TXD signal persists for longer than

tto(dom)TXD, the transmitter is disabled, releasing the bus lines to recessive state. This

function prevents a hardware and/or software application failure from driving the bus lines

to a permanent dominant state (blocking all network communications). The TXD dominant

time-out timer is reset when the CAN_TXD signal is set HIGH. The TXD dominant

time-out time also defines the minimum possible bit rate of 40 kbit/s.

7.12 10-bit ADC

The LPC11Cx2/Cx4 contains one ADC. The ADC is a single 10-bit successive

approximation ADC with eight channels.

7.12.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 V to VDD.

• 10-bit conversion time  2.44 s (up to 400 kSamples/s).

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

7.13 General purpose external event counter/timers

The LPC11Cx2/Cx4 includes two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.13.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

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