DS5000FP

5 of 22

PIN DESCRIPTION (continued)

PIN

NAME

FUNCTION

11, 9, 7, 5, 1,

79, 77, 75

P0.0–P0.7

General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1.

It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data

bus. When used in this mode, it does not require pullups.

13, 14

Power Supply, +5V

16, 8, 18, 80,

76, 4, 6, 20, 24,

26, 28, 30, 33,

35, 37

BA14–

BA0

Byte-Wide Address Bus Bits 14–0. This 15-bit bus is combined with the

nonmultiplexed data bus (BD7–BD0) to access NV SRAM. Decoding is

W. BA14–BA0

connect directly to an 8k or 32k SRAM. If an 8k RAM is used, BA13 and BA14

are unconnected. Note: BA13 and BA14 are inverted from the true logical address.

BA14 is lithium backed.

71, 69, 67, 65,

61, 59, 57, 55

BD7–BD0

Byte-Wide Data Bus Bits 7–0. This 8-bit bidirectional bus is combined with the

nonmultiplexed address bus (BA14–BA0) to access NV SRAM. Decoding is

W. BD7–BD0

connect directly to an 8k or 32k SRAM, and optionally to a real-time clock.

10

R/

W

Read/Write (Active Low). This signal provides the write enable to the SRAMs

on the byte-wide bus. It is controlled by the memory map and partition. The

blocks selected as Program (ROM) is write protected.

74

CE1

Active-Low Chip Enable 1. This is the primary decoded chip enable for memory

access on the byte-wide bus. It connects to the chip enable input of one SRAM.

CE1

78

CE2

Active-Low Chip Enable 2. This chip enable is provided to bank switch to a

second block of 32k bytes of nonvolatile data memory. It connects to the chip

enable input of one SRAM or one lithium-backed peripheral such a real-time

12

SRAM.

54

2, 3, 22, 23, 32,

42, 43, 62, 63,

72

N.C.

No Connection. Do not connect.