TJ2997GD datasheet(12/13 Pages) HTC

12 / 13 page

DDR Termination Regulator

TJ2997

Apr, 2011 - R1.0.1

12/13

HTC

configuration is that it has the ability to source and sink a higher maximum continuous current. PVIN can

be also connected to a 1.8V rail and it has a limitation of maximum continuous current. PVIN should be

connected to a voltage higher than a 1.5V rail. The source/sink current for each power rail, refer to

Electrical Characteristics Section. At any power rail, care should be taken to do not exceed the

maximum junction temperature as the thermal dissipation increases with lower VTT output voltages as

described at the Thermal Dissipation Section.

FIGURE 9. HSTL Application

QDR APPLICATIONS

Quad data rate (QDR) applications utilize multiple channels for improved memory performance.

However, this increase in bus lines has the effect of increasing the current levels required for termination.

The recommended approach in terminating multiple channels is to use a dedicated TJ2997 for each

channel. This simplifies layout and reduces the internal power dissipation for each regulator. Separate

VREF signals can be used for each DIMM bank from the corresponding regulator with the chipset

reference provided by a local resistor divider or one of the TJ2997 signals. Because VREF and VTT are

expected to track and the part to part variations are minor, there should be little difference between the

reference signals of each TJ2997.

FIGURE 10. Typical SSTL-2 Application Circuit

OUTPUT CAPACITOR SELECTION

For applications utilizing the TJ2997 to terminate SSTL-2 I/O signals the typical application circuit

shown in Figure 8 can be implemented. This circuit permits termination in a minimum amount of board

space and component count. Capacitor selection can be varied depending on the number of lines

terminated and the maximum load transient. However, with motherboards and other applications where

TJ2997GD Datasheet(PDF) 12 Page - HTC Korea TAEJIN Technology Co.