12 - 4

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12

HMC680LP4 / 680LP4E

v03.0609

BiCMOS MMIC 5-BIT DIGITAL

VARIABLE GAIN AMPLIFIER, 30 - 400 MHz

Absolute Maximum Ratings

rf input power

20 dbm

rf Output power

22 dbm

digital inputs (b0-b4, latch enable)

-0.5 to Vdd +0.5V

bias Voltage (Vdd)

5.6 V

Channel temperature

125 °C

Continuous pdiss (t = 85 °C)

(derate 42 mW/°C above 85 °C)

1.7 W

thermal resistance

(channel to ground paddle)

24 °C/W

storage temperature

-65 to +150 °C

Operating temperature

-40 to +85 °C

eleCtrOstatiC sensitiVe deViCe

ObserVe Handling preCaUtiOns

Amp Bias Voltage

idd (typ.) (ma)

5V

244

attenUatiOn (db)

b2

b1

b0

0

0

0

0

0

0

1

0

0

0

0

1

2

0

0

0

1

0

3

0

0

0

1

1

4

0

0

1

0

0

5

0

0

1

0

1

6

0

0

1

1

0

7

0

0

1

1

1

8

0

1

0

0

0

9

0

1

0

0

1

10

0

1

0

1

0

11

0

1

0

1

1

12

0

1

1

0

0

13

0

1

1

0

1

14

0

1

1

1

0

15

0

1

1

1

1

16

1

X

0

0

0

17

1

X

0

0

1

18

1

X

0

1

0

19

1

X

0

1

1

20

1

X

1

0

0

21

1

X

1

0

1

22

1

X

1

1

0

23

1

X

1

1

1

[1] enabling b4 disables b3, the minimum attenuation is 16 db

Truth Table

Harmonics vs. Frequency

Supply Current vs. Temperature

-100

-80

-60

-40

-20

0

0

0.1

0.2

0.3

0.4

0.5

0.6

2nd Harmonic

3rd Harmonic

FREQUENCY (GHz)

200

220

240

260

280

4.5

5

5.5

-40C

+25C

+85C

VOLTAGE (V)

Control Interface:

the gain of HmC680lp4(e) is controlled by adjusting the state of the attenuator. the attenuator has a 5-bit parallel

CmOs/ttl compatible interface. state of the attenuator can be set with respect to the truth table above.

Power on sequence:

the ideal power up sequence is: gnd, Vdd, digital inputs, rf inputs. relative order of the digital inputs is not

important as long as they are powered after Vdd/gnd.

Control Voltage Table

state

Vdd = +3V

Vdd = +5V

low

0 to 0.5V @ <1 µa

0 to 0.8V @ <1 µa

High

2 to 3V @ <1 µa

2 to 5V @ <1 µa