Micrel, Inc.

SY898535L

June 2011

3

M9999-062211-B

hbwhelp@micrel.com

Pin Configuration

20-Pin TSSOP (K4-20-1)

Pin Description

Pin Number

Pin Name

Pin Function

1

Ground.

2

CLK_EN

Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q3 outputs. It is

internally connected to a 51kΩ pull-up resistor and will default to a logic HIGH state if left open.

When disabled, Q goes LOW and /Q goes HIGH. CLK_EN being synchronous, outputs will be

1.5V.

3

CLK_SEL

Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the input to the

multiplexer. If HIGH, selects CLK1 input. When LOW, it selects CLK0 input. Note that this input

is internally connected to a 51kΩ pull-down resistor and will default to logic LOW state if left

4

CLK0

Single-Ended Input: This LVCMOS or LVTTL signal is the input signal to the device. It is

internally connected to a 51kΩ pull-down resistor and will default to a logic LOW state if left

open. This input is selected when CLK_SEL is set to logic LOW.

6

CLK1

Single-Ended Input: This LVCMOS or LVTTL signal is the input signal to the device. It is

internally connected to a 51kΩ pull-down resistor and will default to a logic LOW state if left

open. This input is selected when CLK_SEL is set to logic HIGH.

5, 7, 8, 9

NC

Unused Pins

10, 13, 18

VCC

pins as possible.

20, 19

17, 16

15, 14

12, 11

Q0, /Q0

Q1, /Q1

Q2, /Q2

Q3, /Q3

LVPECL Differential Output Pairs: Differential buffered output copies the selected input signal.

The output swing is typically 800mV. Unused output pairs may be left floating with no impact on

jitter. These differential LVPECL outputs are a logic function of the CLK0 and CLK1 inputs. See

“Truth Table” below.

or (408) 955-1690