GS9076 Data Sheet

44617 - 1

January 2008

18 of 25

4.4 Frequency Acquisition Loop — The Phase-Frequency Detector

An external crystal of 14.140 MHz is used as a reference to keep the VCO centered

at the last known data rate. This allows the device to achieve a fast synchronous

lock, especially in cases where a known data rate is interrupted. The crystal

reference is also used to clock internal timers and counters. To keep the optimal

performance of the reclocker over all operating conditions, the crystal frequency

must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is

available from GENNUM.

The VCO is divided by a selected ratio which is dependant on the input data rate.

The resultant is then compared to the crystal frequency. If the divided VCO

frequency and the crystal frequency are within 1% of each other, the PLL is

considered to be locked to the input data rate.

4.5 Phase Acquisition Loop — The Phase Detector

The phase detector is a digital quadrature phase detector. It indicates whether the

input data is leading or lagging with respect to a clock that is in phase with the VCO

(I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop)

is locked, the input data transition is aligned to the falling edge of I-clk and the

output data is re-timed on the rising edge of I-clk. During high input jitter conditions

(>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra

phase correction signals will be generated which instructs the charge pump to

create larger frequency corrections for the VCO.

Figure 4-2: Phase Detector Characteristics

When the PA loop is active, the crystal frequency and the incoming data rate are

compared. If the resultant is more that 2%, the PLL is considered to be unlocked

and the system jumps to the FA loop.

i-PHASE ALIGNMENT

EDGE

DATA RE-TIMING

EDGE

q-PHASE ALIGNMENT

EDGE

0.25UI

0.8UI

I-clk

q-clk

INPUT DATA

WITH JITTER

RE-TIMED

OUTPUT DATA