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82RIA80MPBF Datasheet(PDF) 2 Page - Vishay Siliconix

Part # 82RIA80MPBF
Description  Phase Control Thyristors (Stud Version), 80 A
PDF  8 Pages
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

82RIA80MPBF Datasheet(HTML) 2 Page - Vishay Siliconix

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www.vishay.com
For technical questions within your region, please contact one of the following:
Document Number: 94392
2
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
Revision: 17-Sep-10
80RIA...PbF, 81RIA...PbF, 82RIA...PbF Series
Vishay Semiconductors
Phase Control Thyristors
(Stud Version), 80 A
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum average on-state current
at case temperature
IT(AV)
180° conduction, half sine wave
80
A
85
°C
Maximum RMS on-state current
IT(RMS)
DC at 75 °C case temperature
125
A
Maximum peak, one-cycle
non-repetitive surge current
ITSM
t = 10 ms
No voltage
reapplied
Sinusoidal half wave,
initial TJ = TJ maximum
1900
t = 8.3 ms
1990
t = 10 ms
100 % VRRM
reapplied
1600
t = 8.3 ms
1675
Maximum I2t for fusing
I2t
t = 10 ms
No voltage
18
kA2s
t = 8.3 ms
16
t = 10 ms
100 % VRRM
reapplied
12.7
t = 8.3 ms
11.7
Maximum I2
t for fusing
I2
t
t = 0.1 ms to 10 ms, no voltage reapplied
180.5
kA2
s
Low level value of threshold voltage
VT(TO)1
(16.7 % x
 x I
T(AV) < I <  x IT(AV)), TJ = TJ maximum
0.99
V
High level value of threshold voltage
VT(TO)2
(I >
 x I
T(AV)), TJ = TJ maximum
1.13
Low level value of on-state slope resistance
rt1
(16.7 % x
 x I
T(AV) < I <  x IT(AV)), TJ = TJ maximum
2.29
m
High level value of on-state slope resistance
rt2
(I >
 x I
T(AV)), TJ = TJ maximum
1.84
Maximum on-state voltage
VTM
Ipk = 250 A, TJ = 25 °C, tp = 10 ms sine pulse
1.60
V
Maximum holding current
IH
TJ = 25 °C, anode supply 12 V resistive load
200
mA
Typical latching current
IL
400
SWITCHING
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum non-repetitive rate of
rise of turned-on current
dI/dt
TJ = 125 °C, Vd = Rated VDRM, ITM = 2 x dI/dt snubber
0.2 μF, 15
, gate pulse: 20 V, 65 , t
p = 6 μs, tr = 0.5 μs
Per JEDEC standard RS-397, 5.2.2.6.
300
A/μs
Typical delay time
td
Gate pulse: 10 V, 15
 source, t
p = 6 μs, tr = 0.1 μs,
Vd = Rated VDRM, ITM = 50 Adc, TJ = 25 °C
1
μs
Typical turn-off time
tq
ITM = 50 A, TJ = TJ maximum, dI/dt = - 5 A/μs, VR = 50 V,
dV/dt = 20 V/μs, gate bias: 0 V 25
, t
p = 500 μs
110
BLOCKING
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum critical rate of rise of
off-state voltage
dV/dt
TJ = 125 °C exponential to 67 % rated VDRM
500
V/μs
Maximum peak reverse and
off-state leakage current
IRRM,
IDRM
TJ = 125 °C rated VDRM/VRRM applied
15
mA



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