FM21L16 datasheet(11/15 Pages) RAMTRON

11 / 15 page

FM21L16 - 128Kx16 FRAM

Rev. 2.0

Apr. 2011

Page 11 of 15

Power Cycle and Sleep Mode Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)

Symbol

Parameter

Min

Max

Units

Notes

tPU

Power Up (after VDD min. is reached) to First Access Time

450

µs

tPD

Last Write (/WE high) to Power Down Time

µs

tVR

VDD Rise Time

µs/V

1,2

tVF

VDD Fall Time

100

µs/V

1,2

tZZH

/ZZ Active to DQ Hi-Z Time

tWEZZ

Last Write to Sleep Mode Entry Time

µs

tZZL

/ZZ Active Low Time

µs

tZZEN

Sleep Mode Entry Time (/ZZ low to /CE don’t care)

µs

tZZEX

Sleep Mode Exit Time (/ZZ high to 1st access after wakeup)

450

µs

Notes

Slope measured at any point on VDD waveform.

Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict

when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than

100ms through the range of 0.4V to 1.0V.

Data Retention (VDD = 2.7V to 3.6V)

Parameter

Min

Units

Notes

Data Retention

Years

AC Test Conditions

Input Pulse Levels

0 to 3V

Input and Output Timing Levels

1.5V

Input Rise and Fall Times

3 ns

Output Load Capacitance

30pF

Read Cycle Timing 1 (/CE low, /OE low)

Read Cycle Timing 2 (/CE-controlled)

FM21L16 Datasheet(PDF) 11 Page - Ramtron International Corporation

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