AN601

Vishay Siliconix

Document Number: 70572

15-Feb-94

www.vishay.com

S FaxBack 408-970-5600

5

Test Results

The Siliconix avalanche-rated SMP30N10 is one of a family of

dense-cell MOSPOWER FETs. Cell density for this family is

UIS avalanche breakdown was examined at a variety of

inductance values (0.01 to 10 mH) at starting temperatures

from ambient (25

_C) to 150_C in 25_C increments. A sample

size of 20 pieces for each inductance and at each temperature

involved over 760 MOSFETs. All MOSFETs were from the

same wafer lot.

immediately prior to switching. The equipment used, a ITC UIS

0.1-A increments to 26 A and thereafter in 1.0-A increments.

A fixed gate-drive impedance of 25

W drove the device under

test. A temperature-controlled heater was used to sink the

power MOSFET (mounted in the TO-220 package) to provide

a precise starting temperature throughout the UIS tests.

Temperature (

_C)

80

50

0

0

25

175

30

20

50

75

150

125

100

70

60

40

10

FIGURE 5. Avalanche Failure Current vs. Starting

Temperature for the SMP30N10

L = 0.05 mH

L = 0.1 mH

L = 0.3 mH

L = 1.0 mH

L = 3.0 mH

L = 10 mH

Figure

5

shows

avalanche

current

versus

starting

temperature for six values of inductance, ranging from 0.05 to

10 mH. These data represent single-event UIS failures and

further identify that the device ratings, in particular the

For any given inductance, the avalanche failure current

decreased as the starting temperature increased, although not

as dramatically nor with the tight convergence described by

incremental increases in avalanche current, these data

conclusively show that if Siliconix avalanche-rated power

MOSFETs are operated within data sheet limits, they can enter

into avalanche without fear of failure. Furthermore, these data

tend to confirm that absolute maximum ratings are not so

absolute as once thought. At the 150

_C starting temperature

and switching 32 A (at 1 mH), the calculated chip temperature,

see equation (4), is 322

_C!

The typical 2.2 mV/

resistance of the p-doped region with increasing temperature

suggests that the parasitic npn bipolar transistor becomes

more susceptible to turn-on with increasing temperature.

Although a rapid fall-off of avalanche current at higher

temperatures might be anticipated because of this increased

susceptibility, Figure 5 shows a reasonably slow decline. This

behavior is attributed to the slow lateral spreading of the

current along the p/n junction as the avalanche current

increases. The dense cell design diminishes lateral spreading

of avalanche current beyond the heavily doped p+ (Zener)

region and, thus, enables more avalanche current than

MOSFETs with less dense cell structures.

The measured data (see Figure 5) may be manipulated, with

the help of equation (2), to identify interesting details of UIS

phenomenon. Figure 6 plots avalanche failure current versus

inductance across a temperature range from ambient to

150

_C.

100

1

0.01

0.1

1.0

10

10

25

_C

150

_C

Inductance (mH)

FIGURE 6. Avalanche Failure Current vs. Inductance

for the SMP30N10

*Integrated Technology Corporation, 1228 N. Stadem Drive, Tempe, Arizona 85281