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HT16L21 Datasheet(PDF) 20 Page - Holtek Semiconductor Inc |
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HT16L21 Datasheet(HTML) 20 Page - Holtek Semiconductor Inc |
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20 / 36 page  Rev. 1.00 20 November 16, 2011 HT16L21 Display RAM Page Write Operation AfteraSTARTconditiontheslaveaddresswiththeR/Wbitisplacedonthebusfollowedwithadisplaydatainput commandbyteandthespecifieddisplayRAMRegisterAddressofwhichthecontentsarewrittentotheinternal addresspointer.Thedatatobewrittentothememorywillbetransmittednextandthentheinternaladdresspointer willbeincrementedby1toindicatethenextmemoryaddresslocationafterthereceptionofanacknowledgeclock pulse.Aftertheinternaladdresspointreachesthemaximummemoryaddress,theaddresspointerwillberesetto 00H. Slave Address ACK Write ACK S 0 1 1 1 0 0 0 0 ACK 2nd ACK Data byte P D7 D6 D5 D4 D3 D2 D1 D0 Nth data Data byte D7 D6 D5 D4 D3 D2 D1 D0 2nd data ACK ACK Data byte D7 D6 D5 D4 D3 D2 D1 D0 1st data ACK Register Address byte Command byte 1st 0 0 0 0 0 0 0 1 A0 A1 A2 A3 X X X X I2C Interface N Bytes Display RAM Data Write Operation SP1 SP0 Maximum Memory Address 0 X 0FH 1 0 0DH 1 1 0BH I2C Interface Display RAM Read Operation Inthismode,themasterreadstheHT16L21dataaftersettingtheslaveaddress.FollowingtheR/Wbit(="0") isanacknowledgebit,acommandbyteandtheregisteraddressbytewhichiswrittentotheinternaladdress pointer.AfterthestartaddressoftheReadOperationhasbeenconfigured,anotherSTARTconditionandtheslave addresstransferredonthebusfollowedbytheR/Wbit(="1").ThentheMSBofthedatawhichwasaddressedis transmittedfirstontheI2Cbus.Theaddresspointerisonlyincrementedby1afterthereceptionofanacknowledge clock.ThatmeansthatifthedeviceisconfiguredtotransmitthedataattheaddressofAN+1,themasterwillread andacknowledgethetransferrednewdatabyteandtheaddresspointerisincrementedtoAN+2.Aftertheinternal addresspointerreachesthemaximummemoryaddress,theaddresspointerwillberesetto00H. ThiscycleofreadingconsecutiveaddresseswillcontinueuntilthemastersendsaSTOPcondition. ACK Write ACK P Slave Address S 0 1 1 1 0 0 0 0 Data byte NACK D7 D6 D5 D4 D3 D2 D1 D0 1st data Data byte ACK P D7 D6 D5 D4 D3 D2 D1 D0 Nth data Data byte D7 D6 D5 D4 D3 D2 D1 D0 2nd data ACK ACK ACK Slave Address Read S 0 1 1 1 0 0 0 1 ACK Register Address byte Command byte 1st 2nd A0 A1 A2 A3 X X X X 0 0 0 0 0 0 0 1 0 I2C Interface N Bytes Display RAM Data Read Operation |
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