SI9130CG datasheet(13/15 Pages) VISHAY

13 / 15 page

Document Number: 70190

S11-0975-Rev. G, 16-May-11

www.vishay.com

Vishay Siliconix

Si9130

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

DESIGN CONSIDERATIONS

Inductor Design

Three specifications are required for inductor design:

inductance (L), peak inductor current (ILPEAK), and coil

resistance (RL). The equation for computing inductance is:

Where: VOUT = Output voltage (3.3 V or 5 V);

VIN(MAX) = Maximum input voltage (V);

f = Switching frequency, normally 300 kHz;

IOUT = Maximum dc load current (A);

LIR = Ratio of inductor peak-to-peak ac current to average dc

load current, typically 0.3.

When LIR is higher, smaller inductance values are

acceptable, at the expense of increased ripple and higher

losses.

The peak inductor current (ILPEAK) is equal to the steady-

state load current (IOUT) plus one half of the peak-to-peak ac

current (ILPP). Typically, a designer will select the ac inductor

current to be 30 % of the steady-state current, which gives

ILPEAK equal to 1.15 times IOUT.

The equation for computing peak inductor current is:

OUTPUT CAPACITORS

The output capacitors determine loop stability and ripple

voltage at the output. In order to maintain stability, minimum

capacitance and maximum ESR requirements must be met

according to the following equations:

and,

Where: CF = Output filter capacitance (F)

VREF = Reference voltage, 3.3 V;

VOUT = Output voltage, 3.3 V or 5 V;

RCS = Sense resistor ();

GBWP = Gain-bandwidth product, 60 kHz;

ESRCF = Output filter capacitor ESR ().

Both

minimum

capacitance

and

maximum

ESR

requirements must be met. In order to get the low ESR, a

capacitance value of two to three times greater than the

required minimum may be necessary.

The equation for output ripple in continuous current mode is:

The equations for capacitive and resistive components of the

ripple in pulse-skipping mode are:

The total ripple, VOUT(RPL), can be approximated as follows:

if VOUT(RPL)(R) < 0.5 VOUT(RPL)(C),

then VOUT(RPL) = VOUT(RPL)(C),

otherwise, VOUT(RPL) = 0.5 VOUT(RPL)(C) +

VOUT(RPL)(R).

Lower Voltage Input

The application circuit shown here can be easily modified to

work with 5.5 V to 12 V input voltages. Oscillation frequency

should be set at 200 kHz and increase the output

capacitance to 660 µF on the 5 V output to maintain stable

performance up to 2 A of load current. Operation on the

3.3 V supply will not be affected by this reduced input

voltage.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-

nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability

data, see www.vishay.com/ppg?70190.

OUT

IN(MAX)- VOUT

IN(MAX)

(f) I

OUT

(LIR)

LPEAK

OUT

IN(MAX) - VOUT

(2)(f)(L) V

IN(MAX)

REF

OUT RCS (2)(π)(GBWP)

ESR

OUT RCS

REF

OUT(RPL)

LPP(MAX)

ESR

2x f

OUT(RPL)(C)

(4) 10- 4 (L)

2 C

OUT

IN - VOUT

Volts

OUT(RPL)(R)

(0.02) ESR

Volts

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