SIP11203 datasheet(6/18 Pages) VISHAY

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

DETAILED OPERATION

SUPPLY VOLTAGE (VIN)

The SiP11203/SiP11204 are designed to operate at an

input voltage (VIN) between 5.5 V and 13 V. The

synchronous rectifier drivers (OUTA and OUTB) are

powered directly from VIN, to facilitate setting the gate

drive voltage for the rectifier MOSFETs. Due to the

high peak currents available from the SiP11203/

SiP11204 outputs, careful attention must be paid to the

bypassing of VIN to PGND.

Internal Supply (VL)

In order to provide the internal circuitry of the

SiP11203/SiP11204 with a stable supply voltage (VL),

the SiP11203/SiP11204 incorporate a linear pre-

regulator. Operating from VIN, the pre-regulator

provides a fixed VL of 5 V for use by the majority of the

chip. VL is regulated by VREFINT, and therefore does

not depend upon the voltage at the VREF pin. For

proper IC operation, a bypass capacitor on the order

of 1µF should be connected between VL and GND.

In normal operation, VL is intended to accommodate

the internal light load requirements, such as bias

networks and the sourcing capability of the error

amplifier’s output.

Start-up Considerations

The average pre-regulator output current available to

charge the VL bypass capacitor, and the value of that

capacitor, play an important part in the start-up

sequencing of the SiP11203/SiP11204. Until VL

reaches the Chip Undervoltage Lockout threshold

(CUVLO), the part is held in a low-current standby

state. When VL exceeds the CUVLO voltage of 3.55 V,

the majority of the on-chip circuitry is enabled, with the

exception of the reference voltage buffer and the

output drivers (OUTA and OUTB). Finally, when the

main Undervoltage Lockout threshold (UVLOR) is

reached, which occurs when VL reaches 90 % of its

final value, the VREF buffer and the output drivers are

enabled. This in turn allows the VREF pin to source

current, and the outputs to respond to the INA and INB

inputs. See Figure 4, in the Applications Information

Section.

The I-V characteristic of the pre-regulator approximates

that of a constant current source. With VIN = 7.5 V, the

typical IOUT at the VL pin for voltages between 0 V and

the final regulated voltage of 5 V is 35 mA.

REFERENCE VOLTAGE (VREF)

The

SiP11203/SiP11204

incorporate

internal

voltage reference of 2.5 V. This is scaled and buffered

to drive the VREF pin at 1.225 V. The accuracy of VREF

is ± 1 % at 25 °C, with a temperature coefficient of

160 µV/°C, yielding a worst-case accuracy over

temperature of ± 3 % (- 40 °C to + 85 °C).

Start-up and Soft-Start Considerations

VREF is held at 0 V until VL has exceeded its UVLOR

threshold. This allows a soft-start function to be

implemented by controlling the rate of rise of voltage

on the VREF pin, which in turn causes a gradual rise in

the target voltage of the error amplifier and its

associated voltage control loop. See Figure 4, in the

Applications Information Section.

The charging rate (dV/dt) of VREF is user-settable by

choice of VREF bypass capacitor value. The I-V

characteristic of the reference output approximates

that of a constant current source, with the typical IOUT

at the VREF pin for voltages between 0 V and the final

regulated voltage of 1.225 V being 410 µA. See the

graph “VREF Start-up.”

ERROR AMPLIFIER

The error amplifier is biased from the internal 5 V

supply (VL). The input common mode range extends

down to ground and up to 3.5 V. The output stage can

source in excess of 4 mA and can sink 1 mA. The

output stage is comprised of a class-A source follower

working into a 1 mA pull down (current sink), and is

designed to drive light loads such as an optocoupler

and the series resistor. The output source current IOH

is limited by an internal 500

 resistor, to protect the

output in the event of a short to GND. When sourcing

current in excess of 1 mA, the voltage drop across this

resistor should be taken into account (see graph of

VOH vs. ILOAD). The 1 MHz amplifier has 75 degrees of

phase margin, and a large signal slew rate is (1 V/µs)

in a unitygain configuration. The input offset voltage is

typically 3 mV at 25 °C, and the offset voltage

temperature coefficient is typically 30 uV/°C. Due to its

CMOS inputs, the amplifier has low input bias and

offset currents. Both amplifier inputs as well as the

output are accessible, to facilitate meeting the

compensation requirements of specific applications.

Note that the error amplifier output is clamped low until

the VL voltage has increased past the CUVLOR

voltage level.

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