SMOMAPL138B datasheet(2/281 Pages) TI

2 / 281 page

SMOMAPL138B-HiRel

SLVSAQ9 – JANUARY 2011

www.ti.com

– Hardware Support for Modulo Loop

• USB 1.1 OHCI (Host) With Integrated PHY

Operation

(USB1)

– Protected Mode Operation

• USB 2.0 OTG Port With Integrated PHY (USB0)

– Exceptions Support for Error Detection and

– USB 2.0 High-/Full-Speed Client

Program Redirection

– USB 2.0 High-/Full-/Low-Speed Host

• Software Support

– End Point 0 (Control)

– TI DSP/BIOS™

– End Points 1,2,3,4 (Control, Bulk, Interrupt or

– Chip Support Library and DSP Library

ISOC) Rx and Tx

• 128K-Byte RAM Shared Memory

• One Multichannel Audio Serial Port:

• 1.8V or 3.3V LVCMOS IOs (except for USB and

– Two Clock Zones and 16 Serial Data Pins

DDR2 interfaces)

– Supports TDM, I2S, and Similar Formats

• Two External Memory Interfaces:

– DIT-Capable

– EMIFA

– FIFO buffers for Transmit and Receive

•

NOR (8-/16-Bit-Wide Data)

• Two Multichannel Buffered Serial Ports:

•

NAND (8-/16-Bit-Wide Data)

– Supports TDM, I2S, and Similar Formats

•

16-Bit SDRAM With 128 MB Address

– AC97 Audio Codec Interface

Space

– Telecom Interfaces (ST-Bus, H100)

– DDR2/Mobile DDR Memory Controller

– 128-channel TDM

•

16-Bit DDR2 SDRAM With 512 MB

– FIFO buffers for Transmit and Receive

Address Space or

• 10/100 Mb/s Ethernet MAC (EMAC):

•

16-Bit mDDR SDRAM With 256 MB

– IEEE 802.3 Compliant

Address Space

– MII Media Independent Interface

• Three Configurable 16550 type UART Modules:

– RMII Reduced Media Independent Interface

– With Modem Control Signals

– Management Data I/O (MDIO) Module

– 16-byte FIFO

• Video Port Interface (VPIF):

– 16x or 13x Oversampling Option

– Two 8-bit SD (BT.656), Single 16-bit or Single

• LCD Controller

Raw (8-/10-/12-bit) Video Capture Channels

• Two Serial Peripheral Interfaces (SPI) Each

– Two 8-bit SD (BT.656), Single 16-bit Video

With Multiple Chip-Selects

Display Channels

• Two Multimedia Card (MMC)/Secure Digital (SD)

• Universal Parallel Port (uPP):

Card Interface with Secure Data I/O (SDIO)

– High-Speed Parallel Interface to FPGAs and

Interfaces

Data Converters

• Two Master/Slave Inter-Integrated Circuit (I2C

– Data Width on Each of Two Channels is 8- to

Bus™)

16-bit Inclusive

• One Host-Port Interface (HPI) With 16-Bit-Wide

– Single Data Rate or Dual Data Rate Transfers

Muxed Address/Data Bus For High Bandwidth

– Supports Multiple Interfaces with START,

• Programmable Real-Time Unit Subsystem

ENABLE and WAIT Controls

(PRUSS)

• Serial ATA (SATA) Controller:

– Two Independent Programmable Realtime

– Supports SATA I (1.5 Gbps) and SATA II (3.0

Unit (PRU) Cores

Gbps)

•

32-Bit Load/Store RISC architecture

– Supports all SATA Power Management

•

4K Byte instruction RAM per core

Features

•

512 Bytes data RAM per core

– Hardware-Assisted Native Command

•

PRU Subsystem (PRUSS) can be disabled

Queueing (NCQ) for up to 32 Entries

via software to save power

– Supports Port Multiplier and

•

Command-Based Switching

the subsystem in addition to the normal

• Real-Time Clock With 32 KHz Oscillator and

R31 output of the PRU cores.

Separate Power Rail

– Standard power management mechanism

• Three 64-Bit General-Purpose Timers (Each

•

Clock gating

configurable as Two 32-Bit Timers)

•

Entire subsystem under a single PSC

• One 64-bit General-Purpose/Watchdog Timer

clock gating domain

(Configurable as Two 32-bit General-Purpose

– Dedicated interrupt controller

Timers)

– Dedicated switched central resource

SMOMAPL138B Low-Power Applications Processor

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