CP

GND

GAIN

VDD

VSS

CN

GND

NC

1

3

4

2

5

6

7

14

12

11

13

10

9

8

NC

GND

1

3

4

2

12

10

9

11

GND

-IN_L

OUT_L

MUTE

-IN_R

OUT_R

OUT_L

MUTE

GND

GAIN

VDD

OUT_R

RGT PACKAGE

QFN

(TOP VIEW)

PW PACKAGE

TSSOP

(TOP VIEW)

DRV612

SLOS690B

– DECEMBER 2010 – REVISED APRIL 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

TERMINAL ASSIGNMENT

The DRV612 is available in package:

•

14-pin TSSOP package (PW) or 16-pin QFN package (RGT)

PIN FUNCTIONS

PIN

DESCRIPTION

NAME

PW NO.

RGT NO.

-IN_L

1

16

I

Negative input, left channel

OUT_L

2

1

O

Output, left channel

GND

3, 11

2, 3, 10

P

Ground

MUTE

4

4

I

MUTE, active low

VSS

5

5

O

Change Pump negative supply voltage

CN

6

6

I/O

Charge Pump flying capacitor negative connection

NC

7, 8

7. 14, 15

No internal connection

CP

9

8

I/O

Charge Pump flying capacitor positive connection

VDD

10

9

P

Supply voltage, connect to positive supply

Gain set programming pin; connect a resistor to ground.

GAIN

12

11

I

See Table 1 for recommended resistor values

OUT_R

13

12

O

Output, right channel

-IN_R

14

13

I

Negative input, right channel

Thermal Pad

n/a

Thermal Pad

P

Connect to ground

(1)

I = input, O = output, P = power

2

Copyright

© 2010–2011, Texas Instruments Incorporated