9DB423BGLF datasheet(5/19 Pages) IDT

5 / 19 page

IDT®

Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI

1437B - 02/04/10

9DB423B

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI

Absolute Max

Electrical Characteristics - Input/Supply/Common Output Parameters

Symbol

Parameter

Min

Max

Units

VDD_A

3.3V Core Supply Voltage

4.6

VDD_In

3.3V Logic Supply Voltage

4.6

VIL

Input Low Voltage

GND-0.5

VIH

Input High Voltage

VDD+0.5V

Storage Temperature

-65

150

°C

Tambient

Ambient Operating Temp

°C

Tcase

Case Temperature

115

°C

ESD prot

Input ESD protection

human body model

2000

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input High Voltage

VIH

3.3 V +/-5%

VDD + 0.3

Input Low Voltage

VIL

3.3 V +/-5%

GND - 0.3

0.8

Input High Current

IIH

VIN = VDD

-5

IIL1

VIN = 0 V; Inputs with no pull-up resistors

-5

IIL2

VIN = 0 V; Inputs with pull-up resistors

-200

Operating Supply Current

IDD3.3OP

Full Active, CL = Full load;

200

all diff pairs driven

all differential pairs tri-stated

FiPLL

PCIe Mode (Bypass/133/100= 1)

100.00

110

MHz

FiPLL

QPI Mode (Bypass/133/100= M)

133.33

140

MHz

FiBYPASS

Bypass Mode (Bypass/133/100= 0)

400

MHz

Pin Inductance

Lpin

7nH

CIN

Logic Inputs, except SRC_IN

1.5

CINSRC_IN

SRC_IN differential clock inputs

1.5

2.7

1,4

COUT

Output pin capacitance

-3dB point in High BW Mode

MHz

-3dB point in Low BW Mode

0.7

1.4

MHz

PLL Jitter Peaking

tJPEAK

Peak Pass band Gain

1.5

Clk Stabilization

TSTAB

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

1ms

1,2

Input SS Modulation

Frequency

fMODIN

Allowable Frequency

(Triangular Modulation)

kHz

OE# Latency

tLATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

cycles

1,3

Tdrive_DIF_Stop#

tDRVSTP

DIF output enable after

DIF_Stop# de-assertion

1,3

Tdrive_PD#

tDRVPD

DIF output enable after

PD# de-assertion

300

1,3

Tfall

Fall time of PD# and DIF_Stop#

Trise

Rise time of PD# and DIF_Stop#

SMBus Voltage

VMAX

Maximum input voltage

5.5

Low-level Output Voltage

VOL

@ IPULLUP

0.4

Current sinking at VOL

IPULLUP

4mA

SCLK/SDATA

Clock/Data Rise Time

tRSMB

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

SCLK/SDATA

Clock/Data Fall Time

tFSMB

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

SMBus Operating Frequency

fMAXSMB

Maximum SMBus operating frequency

100

kHz

1,5

1Guaranteed by design and characterization, not 100% tested in production.

2See timing diagrams for timing requirements.

5The differential input clock must be running for the SMBus to be active

IDD3.3PD

3Time from deassertion until outputs are >200 mV

Input Low Current

Powerdown Current

PLL Bandwidth

Input Frequency

Capacitance

4SRC_IN input

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