DATA SHEET

MPC9230 REVISION 8 MARCH 29, 2010

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©2010 Integrated Device Technology, Inc.

800MHz Low Voltage PECL Clock Synthesizer

MPC9230

The MPC9230 is a 3.3 V compatible, PLL based clock synthesizer targeted for high perfor-

mance clock generation in mid-range to high-performance telecom, networking and computing

PECL output signals the device meets the needs of the most demanding clock applications.

Features

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Differential PECL output

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LVCMOS compatible control inputs

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On-chip crystal oscillator for reference frequency generation

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Alternative LVCMOS compatible reference clock input

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3.3 V power supply

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Fully integrated PLL

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Minimal frequency overshoot

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Serial 3-wire programming interface

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Parallel programming interface for power-up

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32-lead LQFP and 28-lead PLCC packaging

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32-lead and 28-lead Pb-free package available

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SiGe Technology

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Ambient temperature range -40

°C to +85°C

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Pin and function compatible to the MC12430

Functional Description

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal

M and the PLL post-divider N determine the output frequency.

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M/4 times the external input reference frequency.

Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4,

or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output

divider, and is capable of driving a pair of transmission lines terminated 50

is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure

the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH

transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are

provided on the M[8:0] and N[1:0] inputs and prevent the LVCMOS compatible control inputs from floating.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial

input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will

capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The

TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL

jitter, it is recommended to avoid active signal on the TEST output.

1. The VCO frequency range of 800–1600 MHz is available at an ambient temperature range of 0 to 70°C. At –40 to +85°C, the VCO frequency (output

frequency) is limited to max. 1500 MHz (750 MHz).

MPC9230

800 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

FN SUFFIX

28-LEAD PLCC PACKAGE

CASE 776-02

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

EI SUFFIX

28-LEAD PLCC PACKAGE

Pb-FREE PACKAGE

CASE 776-02

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04