AFS090 datasheet(219/334 Pages) MICROSEMI

219 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 203

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Timing Characteristics

Table 2-144 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+

VIL

VIH

VOL

VOH

IOL IOH

IOSL

IOSH

IIL1

IIH2

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VmA mA

Max.

mA3

Max.

mA3

µA4 µA4

35 mA

–0.3

VREF – 0.1 VREF + 0.1

3.6

0.6

–

35 35

181

268

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

Figure 2-124 • AC Loading

Table 2-145 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

CLOAD (pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

Note:

*Measuring point = Vtrip. See Table 2-90 on page 2-168 for a complete table of trip points.

Test Point

10 pF

GTL+

VTT

Table 2-146 • 3.3 V GTL+

Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.0 V

Speed

Grade

tDOUT

tDP

tDIN

tPY

tEOUT

tZL

tZH

tLZ

tHZ

tZLS

tZHS

Units

Std.

0.66

2.06

0.04

1.59

0.43

2.09

2.06

4.33

4.29

–1

0.56

1.75

0.04

1.35

0.36

1.78

1.75

3.68

3.65

–2

0.49

1.53

0.03

1.19

0.32

1.56

1.53

3.23

3.20

Note:

For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

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