AFS090 datasheet(227/334 Pages) MICROSEMI

227 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 211

Differential I/O Characteristics

Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer

software when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with these standards.

LVDS

Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires

that one data bit be carried through two signal lines, so two pins are needed. It also requires external

resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-132.

The building blocks of the LVDS transmitter–receiver are one transmitter macro, one receiver macro,

three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three

driver resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Figure 2-132 • LVDS Circuit Diagram and Board-Level Implementation

Table 2-168 • Minimum and Maximum DC Input and Output Levels

DC Parameter

Description

Min.

Typ.

Max.

Units

VCCI

Supply Voltage

2.375

2.5

2.625

VOL

Output Low Voltage

0.9

1.075

1.25

VOH

Input High Voltage

1.25

1.425

1.6

IOL 1

Output Low Voltage

0.65

0.91

1.16

IOH 1

Output High Voltage

0.65

0.91

1.16

Input Voltage

2.925

IIL 2,3

Input Low Voltage

μA

IIH 2,4

Input High Voltage

μA

VODIFF

Differential Output Voltage

250

350

450

VOCM

Output Common Mode Voltage

1.125

1.25

1.375

VICM

Input Common Mode Voltage

0.05

1.25

2.35

VIDIFF

Input Differential Voltage

100

350

Notes:

1. IOL/IOH defined by VODIFF/(Resistor Network)

2. Currents are measured at 85°C junction temperature.

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

140

100

ZO = 50

165

–

INBUF_LVDS

OUTBUF_LVDS

FPGA

Bourns Part Number: CAT16-LV4F12

AFS090 Datasheet(PDF) 227 Page - Microsemi Corporation

AFS090 Datasheet(HTML) 227 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL