AFS090 datasheet(229/334 Pages) MICROSEMI

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Fusion Family of Mixed Signal FPGAs

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LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-134.

The building blocks of the LVPECL transmitter–receiver are one transmitter macro, one receiver macro,

three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three

driver resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Timing Characteristics

Figure 2-134 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-171 • Minimum and Maximum DC Input and Output Levels

DC Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

VCCI

Supply Voltage

3.0

3.3

3.6

VOL

Output Low Voltage

0.96

1.27

1.06

1.43

1.30

1.57

VOH

Output High Voltage

1.8

2.11

1.92

2.28

2.13

2.41

VIL, VIH

Input Low, Input High Voltages

3.3

3.6

3.9

VODIFF

Differential Output Voltage

0.625

0.97

0.625

0.97

0.625

0.97

VOCM

Output Common Mode Voltage

1.762

1.98

1.762

1.98

1.762

1.98

VICM

Input Common Mode Voltage

1.01

2.57

1.01

2.57

1.01

2.57

VIDIFF

Input Differential Voltage

300

Table 2-172 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

1.64

1.94

Cross point

–

Note:

*Measuring point = Vtrip. See Table 2-90 on page 2-168 for a complete table of trip points.

187 W

100

ZO = 50

100

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA

Bourns Part Number: CAT16-PC4F12

Table 2-173 • LVPECL

Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Pro I/Os

Speed Grade

tDOUT

tDP

tDIN

tPY

Units

Std.

0.66

2.14

0.04

1.63

–1

0.56

1.82

0.04

1.39

–2

0.49

1.60

0.03

1.22

Note:

For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

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