AFS090 datasheet(125/334 Pages) MICROSEMI

125 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 109

connected between the VAREF and ADCGNDREF pins. The VAREFSEL control pin is used to select the

reference voltage.

ADC Clock

The speed of the ADC depends on its internal clock, ADCCLK, which is not accessible to users. The

ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed of

the ADCCLK in relationship to SYSCLK, based on EQ 15.

EQ 15

TVC: Time Divider Control (0–255)

tADCCLK is the period of ADCCLK, and must be between 0.5 MHz and 10 MHz

tSYSCLK is the period of SYSCLK

The frequency of ADCCLK, fADCCLK, must be within 0.5 Hz to 10 MHz.

The inputs to the ADC are synchronized to SYSCLK. A conversion is initiated by asserting the

ADCSTART signal on a rising edge of SYSCLK. Figure 2-88 on page 2-113 and Figure 2-89 on

page 2-114 show the timing diagram for the ADC.

Acquisition Time or Sample Time Control

Acquisition time (tSAMPLE) specifies how long an analog input signal has to charge the internal capacitor

array. Figure 2-86 shows a simplified internal input sampling mechanism of a SAR ADC.

The internal impedance (ZINAD), external source resistance (RSOURCE), and sample capacitor (CINAD)

form a simple RC network. As a result, the accuracy of the ADC can be affected if the ADC is given

insufficient time to charge the capacitor. To resolve this problem, you can either reduce the source

resistance or increase the sampling time by changing the acquisition time using the STC signal.

EQ 16 through EQ 18 can be used to calculate the acquisition time required for a given input. The STC

signal gives the number of sample periods in ADCCLK for the acquisition time of the desired signal. If the

actual acquisition time is higher than the STC value, the settling time error can affect the accuracy of the

ADC, because the sampling capacitor is only partially charged within the given sampling cycle. Example

acquisition times are given in Table 2-44 and Table 2-45. When controlling the sample time for the ADC

Table 2-42 • VAREF Bit Function

Name

Bit

Function

VAREF

Reference voltage selection

0 – Internal voltage reference selected. VAREF pin outputs 2.56 V.

1 – Input external voltage reference from VAREF and ADCGNDREF

Table 2-43 • TVC Bits Function

Name

Bits

Function

TVC

[7:0]

SYSCLK divider control

Figure 2-86 • Simplified Sample and Hold Circuitry

tADCCLK

41 TVC

()

tSYSCLK

Sample and Hold

ZINAD

CINAD

Rsource

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