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AFS090 Datasheet(PDF) 129 Page - Microsemi Corporation |
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AFS090 Datasheet(HTML) 129 Page - Microsemi Corporation |
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129 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 113 Timing Diagrams Note: *Refer to EQ 15 on page 2-109 for the calculation on the period of ADCCLK, tADCCLK. Figure 2-87 • Power-Up Calibration Status Signal Timing Diagram Figure 2-88 • Input Setup Time SYSCLK ADCRESET CALIBRATE tREMCLR tCK2QCAL tCK2QCAL TVC[7:0] tSUTVC tHDTVC tCAL = 3,840 tADCCLK* tRECCLR SYSCLK ADCSTART t MINSYSCLK t MPWSYSCLK t HDADCSTART t SUADCSTART MODE[3:0] TVC[7:0] STC[7:0] VAREF CHNUMBER[7:0] t SUMODE t SUTVC t SUSTC t SUCHNUM t SUVAREFSEL t HDMODE t HDTVC t HDSTC t HDVAREFSEL t HDCHNUM |
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