AFS090 datasheet(187/334 Pages) MICROSEMI

187 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 171

Detailed I/O DC Characteristics

Table 2-95 • Input Capacitance

Symbol

Definition

Conditions

Min.

Max.

Units

CIN

Input capacitance

VIN = 0, f = 1.0 MHz

CINCLK

Input capacitance on the clock pin

VIN = 0, f = 1.0 MHz

Table 2-96 • I/O Output Buffer Maximum Resistances 1

Standard

Drive Strength

RPULL-DOWN

(ohms) 2

RPULL-UP

(ohms) 3

Applicable to Pro I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

100

300

8 mA

150

12 mA

16 mA

24 mA

2.5 V LVCMOS

4 mA

100

200

8 mA

100

12 mA

16 mA

24 mA

1.8 V LVCMOS

2 mA

200

225

4 mA

100

112

6 mA

8 mA

12 mA

16 mA

1.5 V LVCMOS

2 mA

200

224

4 mA

100

112

6 mA

8 mA

12 mA

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

3.3 V GTL

25 mA

–

2.5 V GTL

25 mA

–

3.3 V GTL+

35 mA

–

2.5 V GTL+

33 mA

–

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCC

, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/soc/techdocs/models/ibis.html.

2. R(PULL-DOWN-MAX) = VOLspec / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

AFS090 Datasheet(PDF) 187 Page - Microsemi Corporation

AFS090 Datasheet(HTML) 187 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL