Drivers for GaAs FET MMIC Switches and Digital Attenuators

Rev. V3

Application Note

M539

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Figure 1. Driver Block Diagram

This effect can be minimized by increasing the gate

voltage. With higher gate voltage, the incident RF

voltage needs to be at a higher level to cause the

same resistance modulation.

The gate voltage

level affects performance in two regards.

First, if the RF signal level is high enough to cause

the resistance to modulate, the insertion loss of the

MMIC may increase, a condition known as com-

pression. The common measurement of this phe-

nomenon is the 1-dB compression point. This is a

measure of the power level where the loss of the

device increases by 1 dB from the low power loss

levels. If the gate voltage increases, the incident

RF power must be higher to cause compression.

The net result is an increase in the 1-dB compres-

sion point, allowing the device to operate at higher

input power levels.

The voltage that biases the

able from -5 V to -8 V and appears directly at the

gate of the GaAs FET.

The second impact occurs in the intermodulation

performance.

The modulation described above

causes the FET to become more non-linear as the

resistance of the GaAs FET acquires a time vary-

ing component.

Modulation increases the distor-

tion of the GaAs FET, degrading the harmonic and

intermodulation performance. Increasing the gate

voltage minimizes the modulation effect for a given

power level.

Since the GaAs FET is a voltage variable resis-

tance from 0 V to pinch-off, it follows that the same

modulation effect may occur at the 0-V bias level.

M/A-COM has found that if a GaAs FET is biased

slightly positive, this effect is minimized.

In this

case, the resistance of the GaAs FET may in-

crease during the negative portion of the incident

RF signal. A small positive offset minimizes this,

improving the intermodulation performance.

The

voltage is referred to in these switch drivers as

being varied from 0 V to +2 V to optimize inter-

modulation performance.

Output Buffer

The final section of the driver is an output buffer

that occurs after the voltage translation and is com-

posed of successively larger buffer stages.

A

GaAs FET MMIC control component usually con-

sists of several FETs with the gates of multiple de-

vices tied together. Since each device has finite

isolation, tying the gates together presents a cross-

talk isolation concern. The standard technique to

minimize this is to add capacitance to ground on

the control lines, shunting any RF energy on the

control lines to ground. The buffering stages are

designed to allow the driver to drive a load capaci-

tance up to 25 pF.

Performance

For guaranteed maximum ratings and performance

over temperature, please refer to the SWD-109 and

SWD-119 datasheet.