13

ECL Pro®

SY100EP195V

Micrel, Inc.

M9999-120505

hbwhelp@micrel.com or (408) 955-1690

FUNCTIONAL DESCRIPTION

SY100EP195V is a programmable delay line, varying the

delay of a PECL or NECL input signal by any amount between

about 2.2ns and 12.2ns. A 10-bit digital control register affords

delay steps of approximately 10ps.

SY100EP195V implements the delay using a multiplexer

chain and a set of fixed delay elements. Under digital control,

various subsets of the delay elements are included in the

signal chain. To simplify interfacing, the 10-bit digital delay

control word interfaces to PECL, CMOS, or TTL interface

standards.

Since multiplexers must appear in the delay path,

SY100EP195V has a minimum delay of about 2.2ns. Delays

below this value are not possible. In addition, when cascading

multiple SY100EP195V to extend the delay range, the

minimum delay is about 2.2ns times the number of

SY100EP195V in cascade. An eleventh control bit, D[10],

along with the CASCADE and /CASCADE outputs and the

SETMIN and SETMAX inputs, simplifies the task of cascading.

Signal Path Logic Standard

The signal path, from IN, /IN to Q, /Q, interfaces to PECL,

LVPECL, or NECL signals, as shown in Table 6. The choice

of signal path logic standard may limit possible choices for

the delay control inputs, D.

Input Enable

The /EN input gates the signal at IN, /IN. When disabled,

the input is effectively gated out, just as if a logic low was

being provided to SY100EP195V.

/EN

Value at Q, /Q

L

IN, /IN Delayed

H

Logic Low Delayed

Table 1. /EN Truth Table

Digital Control Latch

SY100EP195V can capture the digital delay control word

into its internal 11-bit latch, 10 bits for D[0:9], and an extra bit

for the D[10] cascade control. The LEN input controls the

action of this latch, as per Table 2.

Note that the LEN input is always PECL, LVPECL, or

NECL, the same as the IN, /IN signal pair. The 11-bit delay

control word, however, may also be CMOS or TTL.

LEN

Latch Action

L

Pass Through D[0:10]

H

Latch D[0:10]

Table 2. LEN Truth Table

The nominal delay value is based on the binary value in

D[0:9], where D[0] is the least significant bit, and D[9] is the

most significant bit. This delay from IN, /IN to Q, /Q is about:

∆t

2200 10

value D 9:0 , ps

=+

×

[]

()

Digital Control Logic Standard

SY100EP195V may interface either to PECL, CMOS, or TTL

at which the D inputs switch between logic low and logic high.

TTL signals.

Logic Standard

ECL, PECL

VEF

CMOS

No Connect

TTL

1.5V Source

Table 3. Digital Control Standard Truth Table

indicated in Table 4.

Resistor Value

3.3V

1.5kΩ

5.0V

500Ω

Table 4. Resistor Values for TTL Input

Cascade Logic

SY100EP195V is designed to ease cascading multiple

devices in order to achieve a greater delay range. The SETMIN

and SETMAX pins accomplish this, as set out in the

applications section below. SETMIN and SETMAX override

the delay by changing the value in the D latch register. Table

5 lists the action of these pins.

SETMIN

SETMAX

Nominal Delay (ps)

LL

As per D Latch

LH

2200 + 10 × 1024

HL

2200

HH

Not Allowed

Table 5. SETMIN and SETMAX Action