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MAX11101

14-Bit, +5V, 200ksps ADC with 10µA Shutdown

Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling

Serial Interfaces

The MAX11101’s interface is fully compatible with SPI,

QSPI, and MICROWIRE standard serial interfaces.

If a serial interface is available, establish the CPU’s

serial interface as master, so that the CPU generates the

serial clock for the MAX11101. Select a clock frequency

between 100kHz and 4.8MHz:

1) Use a general-purpose I/O line on the CPU to pull CS

low.

2) Activate SCLK for a minimum of 24 clock cycles. The

serial data stream of eight leading zeros followed by

the MSB of the conversion result begins at the fall-

ing edge of CS. DOUT transitions on SCLK’s falling

edge and the output is available in MSB-first format.

Observe the SCLK to DOUT valid timing characteris-

tic. Clock data into the FP on SCLK’s rising edge.

3) Pull CS high at or after the 24th falling clock edge. If

CS remains low, trailing zeros are clocked out after

the 2 sub-bits, S1 and S0.

new conversion by pulling CS low. A conversion can be

aborted by pulling CS high before the conversion ends.

Wait at least 50ns before starting a new conversion.

Data can be output in three 8-bit sequences or continu-

ously. The bytes contain the results of the conversion pad-

ded with eight leading zeros before the MSB. If the serial

clock has not been idled after the sub-bits (S1 and S0) and

CS has been kept low, DOUT sends trailing zeros.

A0

A1

CLK

CHANGE MUX INPUT HERE

CONVERSION

IN1

A0

A1

IN2

IN3

IN4

OUT

ACQUISITION

4-TO-1

MUX

AIN

CS

MAX11101

CS