CC430F6137IRGC datasheet(21/121 Pages) TI

21 / 121 page

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F613x

CC430F612x

CC430F513x

www.ti.com

SLAS554F

– MAY 2009 – REVISED DECEMBER 2011

Port Mapping Controller

The port mapping controller allows the flexible and re-configurable mapping of digital functions to port pins of

ports P1 through P3.

Table 9. Port Mapping, Mnemonics, and Functions

Value

PxMAPy Mnemonic

Input Pin Function (PxDIR.y=0)

Output Pin Function (PxDIR.y=1)

PM_NONE

None

DVSS

Comparator_B output (on TA0 clock

PM_CBOUT0

input)

1(1)

PM_TA0CLK

TA0 clock input

Comparator_B output (on TA1 clock

PM_CBOUT1

input)

2(1)

PM_TA1CLK

TA1 clock input

PM_ACLK

None

ACLK output

PM_MCLK

None

MCLK output

PM_SMCLK

None

SMCLK output

PM_RTCCLK

None

RTCCLK output

PM_ADC12CLK

ADC12CLK output

7(1)

PM_DMAE0

DMA external trigger input

PM_SVMOUT

None

SVM output

PM_TA0CCR0A

TA0 CCR0 capture input CCI0A

TA0 CCR0 compare output Out0

PM_TA0CCR1A

TA0 CCR1 capture input CCI1A

TA0 CCR1 compare output Out1

PM_TA0CCR2A

TA0 CCR2 capture input CCI2A

TA0 CCR2 compare output Out2

PM_TA0CCR3A

TA0 CCR3 capture input CCI3A

TA0 CCR3 compare output Out3

PM_TA0CCR4A

TA0 CCR4 capture input CCI4A

TA0 CCR4 compare output Out4

PM_TA1CCR0A

TA1 CCR0 capture input CCI0A

TA1 CCR0 compare output Out0

PM_TA1CCR1A

TA1 CCR1 capture input CCI1A

TA1 CCR1 compare output Out1

PM_TA1CCR2A

TA1 CCR2 capture input CCI2A

TA1 CCR2 compare output Out2

PM_UCA0RXD

USCI_A0 UART RXD (Direction controlled by USCI - input)

17(2)

PM_UCA0SOMI

USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD

USCI_A0 UART TXD (Direction controlled by USCI - output)

18(2)

PM_UCA0SIMO

USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK

USCI_A0 clock input/output (direction controlled by USCI)

19(3)

PM_UCB0STE

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

PM_UCB0SOMI

USCI_B0 SPI slave out master in (direction controlled by USCI)

20(4)

PM_UCB0SCL

USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0SIMO

USCI_B0 SPI slave in master out (direction controlled by USCI)

21(4)

PM_UCB0SDA

USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0CLK

USCI_B0 clock input/output (direction controlled by USCI)

22(5)

PM_UCA0STE

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

PM_RFGDO0

Radio GDO0 (direction controlled by Radio)

PM_RFGDO1

Radio GDO1 (direction controlled by Radio)

PM_RFGDO2

Radio GDO2 (direction controlled by Radio)

Reserved

None

DVSS

(1)

Input or output function is selected by the corresponding setting in the port direction register PxDIR.

(2)

UART or SPI functionality is determined by the selected USCI mode.

(3)

UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output USCI_B0 will

be forced to 3-wire SPI mode even if 4-wire mode is selected.

(4)

SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin

drives only the logical 0 to VSS level.

(5)

UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output USCI_A0 will

be forced to 3-wire SPI mode even if 4-wire mode is selected.

Submit Documentation Feedback

CC430F6137IRGC Datasheet(PDF) 21 Page - Texas Instruments

CC430F6137IRGC Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL