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PEF2015 Datasheet(PDF) 18 Page - Siemens Semiconductor Group

Part # PEF2015
Description  Mini IOM-2 Controller MICO
PDF  84 Pages
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Manufacturer  SIEMENS [Siemens Semiconductor Group]
Direct Link  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

PEF2015 Datasheet(HTML) 18 Page - Siemens Semiconductor Group

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Semiconductor Group
18
12.97
PEF 2015
Operational Description
3
Operational Description
The MICO, designed as a flexible line-card controller, has the following main
applications:
– Digital line cards, with the CFI typically configured as IOM-2, IOM-1 (MUX) or SLD.
– Analog line cards, with the CFI typically configured as IOM-2 or SLD.
– Intelligent NTs, where the MICO’s ability to configure the CFI as a PCM interface is
utilized.
To operate the MICO the user must be familiar with the device’s microprocessor
interface, interrupt structure and reset logic.
The device is derived from the EPIC core. With some restrictions it is therefore
programmable like the EPIC.
3.1
Microprocessor Interface Operation
The MICO is programmed via an 8-bit parallel interface that can be selected to be
(1) Motorola type, with control signals DS, R/W, and CS.
(2) Siemens / Intel non-multiplexed bus type, with control signals WR, RD,
and CS.
(3) Siemens / Intel multiplexed address/data bus type, with control signals
ALE, WR, RD, and CS.
The selection is performed via supplying address pins A0 and A1 during reset as follows:
Note: When selecting the multiplexed bus mode, it has to be ensured that during a MICO
device reset the A0/ALE pin receives the appropriate level and no ALE transfers
by the
µC affect the interface type selection (refer also to figure 18, page 75).
When using the Siemens / Intel multiplexed interface, the MICO is addressed with even
addresses only (i.e. AD0 always 0), which allows data always to be transferred in the low
data byte. This simplifies the use of 16 bit Siemens / Intel type processors.
For a non-multiplexed bus structure the OMDR:RBS bit is needed in addition to the
address lines A3..0. OMDR:RBS (Register Bank Selection) selects one of two register
banks.
Table 1
Selection of Bus Interface
A1, A0 during reset
Bus Interface
11
Motorola type (1)
00
Siemens / Intel type, non-multiplexed (2)
01 or 10
Siemens / Intel type, multiplexed (3)
Pin A0 will take over the ALE functionality



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