AD5694R datasheet(6/32 Pages) AD

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AD5696R/AD5695R/AD5694R

Data Sheet

Rev. 0 | Page 6 of 32

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1

Table 4.

Parameter2

Min

Max

Unit

Conditions/Comments

2.5

µs

SCL cycle time

0.6

µs

tHIGH, SCL high time

1.3

µs

tLOW, SCL low time

0.6

µs

tHD,STA, start/repeated start condition hold time

100

tSU,DAT, data setup time

t63

0.9

µs

tHD,DAT, data hold time

0.6

µs

tSU,STA, setup time for repeated start

0.6

µs

tSU,STO, stop condition setup time

1.3

µs

tBUF, bus free time between a stop and a start condition

t10

300

tR, rise time of SCL and SDA when receiving

t11

20 + 0.1CB4

300

tF, fall time of SDA and SCL when transmitting/ receiving

t12

LDAC pulse width

t13

400

SCL rising edge to LDAC rising edge

CB4

400

Capacitive load for each bus line

See Figure 2.

Guaranteed by design and characterization; not production tested.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s

falling edge.

CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

Figure 2. 2-Wire Serial Interface Timing Diagram

SCL

SDA

LDAC1

LDAC2

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

t13

t11

t10

t12

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