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AD5791 Datasheet(PDF) 5 Page - Analog Devices

Part # AD5791
Description  System Ready, 18-Bit 짹1 LSB INL
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5791 Datasheet(HTML) 5 Page - Analog Devices

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Data Sheet
AD5780
Rev. C | Page 5 of 28
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit1
Parameter
IOVCC = 1.71 V to 3.3 V
IOVCC = 3.3 V to 5.5 V
Unit
Test Conditions/Comments
t12
40
28
ns min
SCLK cycle time
92
60
ns min
SCLK cycle time (readback and daisy-chain modes)
t2
15
10
ns min
SCLK high time
t3
9
5
ns min
SCLK low time
t4
5
5
ns min
SYNC to SCLK falling edge setup time
t5
2
2
ns min
SCLK falling edge to SYNC rising edge hold time
t6
48
40
ns min
Minimum SYNC high time
t7
8
6
ns min
SYNC rising edge to next SCLK falling edge ignore
t8
9
7
ns min
Data setup time
t9
12
7
ns min
Data hold time
t10
13
10
ns min
LDAC falling edge to SYNC falling edge
t11
20
16
ns min
SYNC rising edge to LDAC falling edge
t12
14
11
ns min
LDAC pulse width low
t13
130
130
ns typ
LDAC falling edge to output response time
t14
130
130
ns typ
SYNC rising edge to output response time (LDAC tied low)
t15
50
50
ns min
CLR pulse width low
t16
140
140
ns typ
CLR pulse activation time
t17
0
0
ns min
SYNC falling edge to first SCLK rising edge
t18
65
60
ns max
SYNC rising edge to SDO tristate (CL = 50 pF)
t19
62
45
ns max
SCLK rising edge to SDO valid (CL = 50 pF)
t20
0
0
ns min
SYNC rising edge to SCLK rising edge ignore
t21
35
35
ns typ
RESET pulse width low
t22
150
150
ns typ
RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.



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