Data Sheet

AD5780

Rev. C | Page 21 of 28

Asynchronous DAC Update

In this mode, LDAC is held high while data is being clocked

into the input shift register. The DAC output is asynchronously

updated by taking LDAC low after SYNC has been taken high.

The update now occurs on the falling edge of LDAC.

Reset Function (RESET)

The AD5780 can be reset to its power-on state by two means:

either by asserting the RESET pin or by using the reset function

in the software control register (see

). If the

Table 13

RESET pin

Asynchronous Clear Function (CLR)

The CLR pin is an active low clear that allows the output to be

cleared to a user defined value. The 18-bit clearcode value is

programmed to the clearcode register (see

). It is

necessary to maintain

Table 12

CLR low for a minimum amount of time

to complete the operation (see

). When the

Figure 2

CLR signal

is returned high, the output remains at the clear value (if LDAC

is high) until a new value is loaded to the DAC register. The

output cannot be updated with a new value while the CLR pin is

low. A clear operation can also be performed by setting the CLR

bit in the software control register (see

).

Table 13

ON-CHIP REGISTERS

DAC Register

Table 9 outlines how data is written to and read from the DAC

register.

The following equation describes the ideal transfer function of

the DAC:

(

)

REFN

REFN

REFP

OUT

V

D

V

V

V

+

×

−

=

18

2

where:

D is the 18-bit code programmed to the DAC.

Table 8. Hardware Control Pins Truth Table

LDAC

CLR

RESET

Function

X1

X

X

1

0

The AD5780 is in reset mode. The device cannot be programmed.

X1

X

X

1

The AD5780 is returned to its power-on state. All registers are set to their default values.

0

0

1

The DAC register is loaded with the clearcode register value, and the output is set accordingly.

0

1

1

The output is set according to the DAC register value.

1

0

1

The DAC register is loaded with the clearcode register value, and the output is set accordingly.

1

1

The output is set according to the DAC register value.

0

1

The output remains at the clearcode register value.

1

1

The output remains set according to the DAC register value.

0

1

The output remains at the clearcode register value.

1

1

The DAC register is loaded with the clearcode register value and the output is set accordingly.

0

1

The DAC register is loaded with the clearcode register value and the output is set accordingly.

1

1

The output remains at the clearcode register value.

0

1

The output is set according to the DAC register value.

Table 9. DAC Register

MSB

LSB

DB23

DB22

DB21

DB20

DB19 to DB2

DB1

DB0

R/W

Register address

DAC register data

R/W

0

0

1

18 bits of data

X1

X

X

1