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ADE7816 Datasheet(PDF) 6 Page - Analog Devices |
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ADE7816 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 48 page  ADE7816 Data Sheet Rev. 0 | Page 6 of 48 SPI Interface Timing Table 3. SPI Interface Timing Parameters Parameter Symbol Min Max Unit SS to SCLK Edge tSS 50 ns SCLK Period 0.4 40001 μs SCLK Low Pulse Width tSL 175 ns SCLK High Pulse Width tSH 175 ns Data Output Valid After SCLK Edge tDAV 100 ns Data Input Setup Time Before SCLK Edge tDSU 100 ns Data Input Hold Time After SCLK Edge tDHD 5 ns Data Output Fall Time tDF 20 ns Data Output Rise Time tDR 20 ns SCLK Rise Time tSR 20 ns SCLK Fall Time tSF 20 ns MISO Disable After SS Rising Edge tDIS 200 ns SS High After SCLK Edge tSFS 0 ns 1 Guaranteed by design. MSB LSB LSB IN INTERMEDIATE BITS INTERMEDIATE BITS tSFS tDIS tSS tSL tDF tSH tDHD tDAV tDSU tSR tSF tDR MSB IN MOSI MISO SCLK SS Figure 3. SPI Interface Timing |
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